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path: root/drivers/gpu/nvgpu/include/nvgpu/hw
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* gpu: nvgpu: fix suspending all SMsCory Perry2017-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In gk20a_suspend_all_sms(), we currently loop over all GPCs and then loop over all TPCs in inner loop But this is incorrect and leads to SM with invalid GPC,TPC ids Fix this by looping over number of TPCs in each GPC in inner loop Also, fix gk20a_gr_wait_for_sm_lock_down() as per below - we right now wait infinitely for SM to lock down - restrict this wait with a timeout on silicon platforms - return ETIMEDOUT instead of EAGAIN - add more debug prints with additional data for SM lock down failures Bug 200258704 Change-Id: Id6fe32e579647fd8ac287a4b2ec80cbf98791e0d Signed-off-by: Cory Perry <cperry@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1316471 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix unicast register accesses for SMTerje Bergstrom2017-02-17
| | | | | | | | | | | | | | | | | In two places we used broadcast register as base, but added the unicast offset to it. This causes the write to go well beyond valid register range. Change the broadcast base to use unicast base instead in sequence to resume a single SM and to record error state of SM. Bug 200256272 Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c) Reviewed-on: http://git-master/r/1306331 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Pull latest gp10b headersPeter Boonstoppel2017-02-14
| | | | | | | | | | | | | HWCL 38000754 Bug 1819874 Change-Id: Ic28bd2abee4caac83c2d21b035a64558d72aa0fa Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1301674 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: enable PCI MSI interruptsDavid Nieto2017-02-08
| | | | | | | | | | | | | | Use MSI interrupts instead of legacy on PCIe dGPUs to reduce latency and contention with other PCIe devices JIRA EVLR-986 Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291758 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix priv ring error detectionTerje Bergstrom2017-01-31
| | | | | | | | | | | | | | | | | | | | | Use hardware headers instead of hardcoded register numbers in priv ring. This required updating the priv ring headers to add all the registers and fields needed. Incidentally this also gets rid of a lot of GPC priv ring registers as they're not used in our code. Also delete duplicate prints for the same information. We were dumping GPC error also in gk20a_pbus_isr(), and we dumped master information twice. Dump status of each GPC separately instead of supporting only GPC0. Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1295481 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: gp106: Generate new gp106 headersTerje Bergstrom2017-01-26
| | | | | | | | | | | | | | Hardware headers have been outdated. Regenerate with newest tool. At the same time correct the incorrect usage of fuse fields. JIRA DNVGPU-172 Change-Id: If190bf0cf2e41d525e6ea374a30efd1f63963e5e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294267 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add GPU reset for gp106 XVEAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | Resets the GPU without resetting the XVE/XP interfaces. This allows the GPU to stay attached to the PCI bus but still resets all the rest of the GPU's internal state. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287644 Reviewed-on: http://git-master/r/1287650 (cherry picked from commit c14efaee5d03a053d5bf229425a7594e1c6bfad0) Change-Id: If7aba3cc8109e30bd6b6aa145836e812d50b35c5 Reviewed-on: http://git-master/r/1292699 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gp106 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gm206 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm206 HW headers to a new directory specially for them: include/nvgpu/hw/gm206 And change the code to include like so: #include <nvgpu/hw/gm206/hw_fb_gm206.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I90dc39e64e1b58ee9e87fbc26ad0d18c361e239c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244792 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move gm20b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm20b HW headers to a new directory specially for them: include/nvgpu/hw/gm20b And change the code to include like so: #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I0765e2f6bcd5aa1e803efd250056de3cf9bfa7ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244791 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Start re-organizing the HW headersAlex Waterman2017-01-11
Reorganize the HW headers of gk20a. The headers are moved to a new directory: include/nvgpu/hw/gk20a And from the code are included like so: #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> This is the first step in reorganizing all of the HW headers for gm20b, gm206, etc. This is part of a larger effort to re-structure and make the driver more readable and scalable. Bug 1799159 Change-Id: Ic151155cbc2e6f75009f2d9d597b364a1bed2c4c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244790 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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