| Commit message (Collapse) | Author | Age |
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Use nvgpu specific nvgpu_kcalloc()/nvgpu_kfree() calls instead of linux specific
kcalloc()/kfree()
Jira NVGPU-259
Change-Id: I73034ea23561d1269230b9ac10360f8b171b8d41
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588221
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Try to fix invalid pte type repalayable faults only.
All other replayable faults will be cancelled so that
next mmu fault for same fault address will be triggered
as non-replayable fault and ch/tsg teardown will take place.
Bug 1958308
Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566576
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Teardown function should be passed appropriate id and
id_type. E.g. if a channel is marked as tsg, channel teardown/rc
function should be passed it's tsgid as id and type_tsg as
id_type
Bug 200277163
Change-Id: I2e83561c03d515fac28cbb8ce75a9f2c7bf746ac
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1557296
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fixups for the change of name subject in nvgpu.
JIRA NVGPU-287
Change-Id: I6c19733079061a42786b94fc48db374d715ccbef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1586548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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t19x changes necessary for change in core MM code.
JIRA NVGPU-30
Change-Id: Id0d66543582abcef522e3182da0b01d0042f4b14
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585476
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Follow the sizing consideration in bug 1753763 to support dynamic TPC modes
and subcontexts.
bug 200350539
Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Make GPU characteristics flags specific to Linux code only. The
rest of driver is moved to using nvgpu_is_enabled() API.
JIRA NVGPU-259
Change-Id: I46a5a90bb34f170e9e755e7683be142ed6b18cce
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583992
GVS: Gerrit_Virtual_Submit
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Create an nvgpu internal nvgpu_gr_sm_error_state to store and
propagate SM error state within driver. Use
nvgpu_dbg_gpu_sm_error_state_record only in Linux code.
JIRA NVGPU-259
Change-Id: Ia2b347d0054365bdc790b4d6f2653a568935bdb0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1585646
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- in the native case, replace calls for init_cyclestats with
the gm20b version, as each chip had identical versions of the code.
- in the virtual case, use the vgpu version of the function in order
to get the new max_css_buffer_size characteristic set to the mempool
size.
JIRA ESRM-54
Bug 200296210
Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578934
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Updated regops whitelist for HW CL 39314184
i.e. snap_0913 and VDK_R11
Change-Id: Ie22f0a000c4bb151023a92e0d7e877bbceb157f2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565684
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Updated clock gating prod settings for HW CL 39314184
i.e. snap_0913 and VDK_R11
Change-Id: Iae6fd9e95ee5e1ec20bafbb24cd761bdce8fdc5f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565683
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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For SCG to work, smid numbering needs to be done
based on scg performance of tpcs. For gv11b and
gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table"
to do this.
Used local variable "index" to avoid multiple computations in
the function: gr_gv100_init_sm_id_table
index = sm_id + sm
Add deug info for printing initialized gpc/tpc/sm/global_tpc
indexs.
Bug 1842197
Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583916
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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t19x changes necessary for change in core MM code.
JIRA NVGPU-30
Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577265
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gv11b should use acr_dmem_desc_v1 instead of acr_dmem_desc.
JIRA GPUT19X-5
Change-Id: I3ccae72541607aec12e25845ea4cb875ff11d67c
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583642
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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With coherency issues solved, it is no longer needed to allocate the fault
buffer in vidmem as a workaround.
JIRA: NVGPUGV100-36
Change-Id: I1c83e9bac61f27b75f38fce963899485afeed009
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582769
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts
need to be adjusted to avoid false positives.
JIRA: NVGPUGV100-36
Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582092
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added method to load mem unlock binary into
nvdec falcon & execute to perform mem unlock
if VPR enabled.
- Updated .mem_unlock gv100 HAL to point
method gv100_fb_memory_unlock().
- Updated .mem_unlock gv11b HAL to NULL.
- Added vpr info hw registers
- Added nvdec enable hw register
Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
(cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb)
Reviewed-on: https://git-master.nvidia.com/r/1573101
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Updated perf_pmasys_mem_block_target in perf_pmasys_mem_block
based on memory aperture used for perfbuf inst_block.
Bug 200327596
Change-Id: Ic3df332a2248c5ea2d6d38ceab8ba04c618ffefc
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1582788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Updated following hal functions for css gv11b and reused
them for gv100:
enable_snapshot
disable_snapshot
check_data_available
These changes are needed because of following reasons:
1. Register offsets for perf_pmasys_* are changed
for gv11b/gv100 from gk20a.
2. Updated memory type for perf_pmasys_mem_block_target
based on memory aperture used for hwpm inst_block.
Bug 200327596
Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1507546
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gr restore_context_header is not required any more after
enabling per context va mode for subcontext. Cleaning-up
unused function pointers from gv100 and gv11b HAL.
Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1581432
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change required for equivalent change on nvgpu. This is required
since a few HALs were added that must be populated for all chips.
This patch adds those HAL definitions for gv11b, gv100, and the
vgpu.
JIRA NVGPU-30
JIRA NVGPU-138
Change-Id: I65374764350a5cacce8624b15d98947fada35a4a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579865
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Updated following hal functions for gv11b and reused
them for gv100:
perfbuffer_enable
perfbuffer_disable
These changes are needed because of following reasons:
1. Register offsets for perf_pmasys_* are changed
for gv11b/gv100 from gk20a.
2. Updated memory type for perf_pmasys_mem_block_target
to sys_ncoh_f().
Bug 200327596
Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571074
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux
specific rw_semaphore.
JIRA NVGPU-259
Change-Id: I5f6c918464315e3d140bea0c61a619c3712619c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1579934
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Replace use of ioctl structure warpstate with internal
nvgpu_warptate.
JIRA NVGPU-259
Change-Id: I003c15152042e566124c04d6124e515e36157c88
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578683
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of calling the native HAL init function then adding
multiple layers of modification for VGPU, flatten out the sequence
so that all entry points are set statically and visible in a
single file.
JIRA ESRM-30
Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574619
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement T19x specific usermode aperture initialization functions.
Move usermode_regs field to nvgpu_os_linux_t19x, because it is
Linux specific.
JIRA NVGPU-259
Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569699
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For sync-point read map, create read only map per vm
and share with all channels that are using same vm.
Now restrict rw map to single syncpoint shim memory range.
JIRA GPUT19X-2
Change-Id: Ibd0b82d1cdb8861e1dbb073b27da1f9c9ab1d2ab
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514339
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 6647e5c9569258fbf3db096275a79f86f86ed3a6.
Bug 200352825
Change-Id: Ia44d61eafce78f99be2271e0afaf69cd5c102080
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577920
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
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Remove phys_addr_t change for corresponding change in the nvgpu
main repo.
JIRA NVGPU-30
JIRA NVGPU-226
Change-Id: I05a19bc51e949279edef6e9ad7161226cbca51a7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1576466
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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These changes allow GV100 to init the basic HALs to pass
nvgpu_submit_twod
(1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency
issues
(2) Properly enable FB
(3) Fan control requires the execution of the pre-os FW, without it the SKU201
is extremely noisy
JIRA: NVGPUGV100-9
Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Will be enabled after feature is verified on volta
Bug 200352825
Change-Id: Idbe318ea82051e53f15caecf2afb15d72b99acea
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574482
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Feature will be enabled after it is verified.
To disable cycle stat, do not set
NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS and
NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT
Bug 200352825
Change-Id: I3f0d58a8095f3a0996964056029c12cff45f0a5b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1573760
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add debug prints to track veid bundle init
and also return err for subctx init failure.
Bug 1983643
Change-Id: I9e6a32e76b1c7deba3a47157ba253976d88b2324
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568070
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify
channel status while unbinding a channel from TSG while closing
Add support to do this verification per-platform and keep this disabled
for vgpu platforms
Bug 200327095
Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1572369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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T19x/gv100 version of same patch in kernel/nvgpu.
Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566750
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For pre-silicon platforms, clock gating
should be skipped as it is not supported.
Added new flags "can_"x"lcg" to check platform
capability before programming SLCG,BLCG and ELCG.
Bug 200314250
Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566251
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter*
and *hubmmu_idle_filter* in therm regs.
Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570556
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Check for memory aperture type before setting relevant
sysmem non-coherent or vidmem flags in ram entry.
Modified following functions to correct memory aperture type:
gv11b_get_ch_runlist_entry
gv11b_subctx_commit_pdb
Added following hw constants for chan_inst_target:
ram_rl_entry_chan_inst_target_sys_mem_coh_v
ram_rl_entry_chan_inst_target_vid_mem_v
Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1569521
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Reading gr_pri_fe_chip_def_info_r() during
gv11b_init_fifo_setup_hw on RTL platforms is giving
"0xbadf1201" error because fecs part of priv ring
is still in reset. This needs to be fixed after
identifying relevant engine that needs to be
brought out of reset. Until that time, use constant
value from hw definition(whose value is 64):
gr_pri_fe_chip_def_info_max_veid_count_init_v().
Bug 1983643
Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implemented litter values for following defines:
GPU_LIT_SMPC_PRI_BASE
GPU_LIT_SMPC_PRI_SHARED_BASE
GPU_LIT_SMPC_PRI_UNIQUE_BASE9
GPU_LIT_SMPC_PRI_STRIDE
Added broadcast flags for smpc
Handled all combinations of broadcast/unicast EGPC, ETPC, SM
Bug 200337994
Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539075
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change license of OS independent source code files to MIT.
JIRA NVGPU-218
Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567804
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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update .read_wpr_info HAL of gv11b & gv100
to point to gm20b_fb_read_wpr_info()
JIRA NVGPU-128
Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564684
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Bug 200348860
Bug 200291879
Change-Id: Ia1e651d8365eae6e7aef69d79923d644c7067211
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563869
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Volta traphandler RM changes
Sm lock-down is not being executed correctly. This results in a
GPU being in an undefined state. A similar bug fix was already
provided on the resman implementation. This fix is inspired by the
CL change 21183102.
That change refers to bug http://nvbugs/1800484 and bug
http://nvbugs/200162542
This patch solves the issues mention in bug http://nvbugs/1992522
Change-Id: I601fef7c94e5ba419d7bf854877fa7a9f9b82cfa
Signed-off-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563815
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Enable per veid header mode for subcontext header.
Allocated only context header size for subcontext
header.
Bug 1958308
Change-Id: I6b45987eed968252326a366650fefd807975b70f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562681
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Initlize following context switch header counters for
gv11b:
ctxsw_prog_main_image_num_save_ops
ctxsw_prog_main_image_num_restore_ops
ctxsw_prog_main_image_num_wfi_save_ops
ctxsw_prog_main_image_num_cta_save_ops
ctxsw_prog_main_image_num_gfxp_save_ops
ctxsw_prog_main_image_num_cilp_save_ops
Reused gp10b gr hal function gr_gp10b_init_ctxsw_hdr_data()
for this.
Bug 1958308
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I10d83e35ccd8cba517ebaba1f0e5bec5a0f68ba5
Reviewed-on: https://git-master.nvidia.com/r/1562655
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Corrected whitelist register address offset for
gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is
changed for gv11b from gp10b. With wrong offset value,
gl tests are generating "unhandled fecs error interrupt
0x00000002 for channel xxx".
Bug 1958308
Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562615
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gv11b_fb_fault_buf_configure_hw is declared twice. Fix
the same by removing one of the declarations.
Change-Id: I12a857b4225164067f0329530249ffc0dcdc1412
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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CTXSW_TRACE will be enabled only after it is
verified. Set all function pointers for fecs_trace
to NULL
JIRA GPUT19X-42
Change-Id: I7a807f997f683c19541e55fa7e3d5d3ff6b645d2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1558464
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use tsgid for polling preemption completion since
id and next_id in pbdma and eng status point to
tsgid
Bug 200277163
Bug 1958308
Change-Id: I5636ce1f8b21ddac4c93d92ce0527fe0307f2cfc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1557253
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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