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* gpu: nvgpu: gv11b: init set_hww_esr_report_maskSeema Khowala2017-06-30
| | | | | | | | | | | | | | gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr* registers instead of *gpcs_tpcs_sm_hww_warp/global_esr* GPUT19X-75 Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1474860 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init record_sm_error_state gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | Take care of t19x sm reg address changes and support multiple SM JIRA GPUT19X-75 Change-Id: I675b76b90d08fe75331f0023f1fe722497d06373 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1477673 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init set_sm_debug_mode gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | | Support multiple SM and take care of sm reg addr changes JIRA GPUT19X-75 Change-Id: Id39e269034762c7a8347edaf1fff0b2efd7f153c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1477705 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init update_sm_error_state gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | Support multiple SM and take care of SM hardware reg address changes JIRA GPUT19X-75 Change-Id: I866011a85da06ca22bc10fda5ab59f84d0782902 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1477686 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init bpt_reg_info gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | Take care of t19x reg address changes to support multiple SM JIRA GPUT19X-75 Change-Id: I92b97e60ac82c50a97fe44a85482437446479800 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1477694 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: init trigger_suspend gr opsSeema Khowala2017-06-30
| | | | | | | | | | | | | | | Add gv11b specific trigger_suspend function. SM register addresses have changed as compared to legacy gpu chips. JIRA GPUT19X-75 Change-Id: Ic3099e53bcba19128711a88ecc9e9883f5f7a31f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1476532 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: dump sm regsSeema Khowala2017-06-30
| | | | | | | | | | | | | | | /d/gpu.0/gr_status will dump sm registers too JIRA GPUT19X-75 Change-Id: If5d19c9ef5c05b6390e8e55c39571869d3d01ae7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1500879 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Corrected sm whitelist addressSeema Khowala2017-06-30
| | | | | | | | | | | | | | | | corrected whitelist address for gr_pri_gpcs_tpcs_sms_dbgr_control0 JIRA GPUT19X-49 Bug 200311674 Change-Id: I512197c4a6ef97a59bbb303e31ab91f7727bf8d5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1499394 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: add fifo_gv11b and usermode_regsRichard Zhao2017-06-30
| | | | | | | | | | | | | | | | - add fifo_gv11b to store usermode_regs - consider channel_base and use usermode_regs when ring channel doorbell It'll make kickoff code re-usable for vgpu. Jira VFND-3796 Change-Id: Ia6974ccac137f201ad8763a7d372de81d5cca56b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1510457 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: rename hw_chid to chidRichard Zhao2017-06-30
| | | | | | | | | | | | | | hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: Ie94c1a15e9e45fc823d85790ce6a69da53a685bf Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509531 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* pu: nvgpu: gv11b: rename write_preemption_ptrseshendra Gadagottu2017-06-29
| | | | | | | | | | | Change function name write_preemption_ptr to set_preemption_buffer_va to match with what exactly getting done in that function. Change-Id: I91372642f1dba37e5e7bcda29ac9c4271cec4b53 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1510973 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU reset reorg supportMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | - Assigned gv11b pmu engine reset & status ops to point to gp106 ops. JIRA NVGPU-99 Change-Id: I6338e2c5a1458e88a62cf0966b59c1dbe73385b6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507884 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: multiple sm supportSeema Khowala2017-06-29
| | | | | | | | | | | | | -Calculate sm reg offset by using gpc, tpc and sm numbers -Init get_esr_sm_sel gr ops JIRA GPUT19X-75 Change-Id: I74cfcae07e385cdad51774b963380c0633adfecf Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1506152 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: sm register changesSeema Khowala2017-06-29
| | | | | | | | | | | | | gv11b has multiple SMs and SM register addresses have changed as compared to legacy chips. JIRA GPUT19X-75 Change-Id: I2319f4c78f3efda3430bab1f5ecf1a068e57a1ca Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1506013 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: reuse gp10b functionsSeema Khowala2017-06-29
| | | | | | | | | | | | reuse gr_gp10b_handle_fecs_error and cilp functions Bug 200289491 Change-Id: I4040f96875ad91d174ce36aab957fb94d79c3a74 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1505952 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: sm stride litter addedSeema Khowala2017-06-29
| | | | | | | | | | | | | | Required to support multiple SM JIRA GPUT19X-75 Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1475985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: Reorganize ltc HAL initializationSunny He2017-06-27
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1507563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBGseshendra Gadagottu2017-06-27
| | | | | | | | | | | | | | | | | | Added sw method for NVC397_SET_TEX_IN_DBG with following data fields: data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST Bug 1934197 Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1507479 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b, use nvgpu_flcn_copy_to_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | | - replace usage of pmu_copy_to_dmem() with nvgpu_flcn_copy_to_dmem() JIRA NVGPU-99 Change-Id: I8d0ce1cb7adffc4df57044b8887d525c1f2f0237 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506582 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement ctxnotvalid pbdma_intr_1Seema Khowala2017-06-27
| | | | | | | | | | | | | | | | | | | | | | | | Pbdma which encountered the ctxnotvalid interrupt will stall and prevent the channel which was loaded at the time the interrupt fired from being swapped out until the interrupt is cleared. CTXNOTVALID pbdma interrupt indicates error conditions related to the *_CTX_VALID fields for a channel. The following conditions trigger the interrupt: * CTX_VALID bit for the targeted engine is FALSE * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE JIRA GPUT19X-47 Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1329372 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: enable sync point supportSeema Khowala2017-06-27
| | | | | | | | | | | JIRA GPUT19X-2 Change-Id: If69567af3f6de6cd65429086578715fb4d6dfeb5 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1323440 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fbhub: num_ltcs are read onlyseshendra Gadagottu2017-06-21
| | | | | | | | | | | | | | | | In gv11b fbhub num_ltcs is read only, even though register spec says it is rw. The number of ltcs are populated by hw and no need for sw to set those values. GPUT19X-70 Change-Id: Ib9861894cacb70cf54b4958083e55d39a3a85e19 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1497992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Merge tegra/linux to common/linuxTerje Bergstrom2017-06-20
| | | | | | | | | | | | | | tegra/linux path was created to separate Tegra kernel specific dependencies from common Linux specific dependencies. The split has not really worked, so merge tegra/linux to common/linux. JIRA NVGPU-38 Change-Id: I9efe078bfa5dfbef49408db9d8a3738dfda8bd1d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1505169 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: make subcontext mappings non-cacheableseshendra Gadagottu2017-06-20
| | | | | | | | | | | | | | | | | | Without non-cacheable, gpu filled subcontext data not visible to cpu without additional l2 flush. Similarly, there will be issues where cpu updates to subcontext header will not visible to gpu without additional l2 flush. Making subcontext header mapping non-cacheable fixes this issue. Bug 1937331 Change-Id: I8e25b7cac165e7481eec7c9f1f93bc7992183c46 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1505283 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fb_flush before/after l2_flushseshendra Gadagottu2017-06-20
| | | | | | | | | | | | | | | | | | | | After enabling l2 write back in gv11b, for committing all dirty data to sysmem correctly: Added one fb_flush before l2_flush to commit dirty hshub data to l2/sysmem. Added one more fb_flush after l2_flush, to commit any new dirty data on hshub to sysmem. This done by implementing gv11b specific l2_flush function. Bug 1937331 Change-Id: Ie30edb12c98c4021783c88750bb4c4ca62e4a7ca Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1503385 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: nvgpu: gv11b: Add/Update PMU cmds for ELPG.Vijayakumar2017-06-20
| | | | | | | | | | | | | | | | | This patch: - Adds a PMU command needed for enabling ELPG. i.e. command to update sub-feature mask to enable ELPG. - Adds a new version of PG-GR init param command function which uses updated command interface. JIRA GPUT19X-20. Change-Id: If969c018e2e28264fdc9c897892eb28b021d12f2 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1504873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: PMU PG reorg support updateMahantesh Kumbar2017-06-13
| | | | | | | | | | | | | - Prepend ELPG enable/disable methods with nvgpu_ by replacing gk20a_ in gv11b JIRA NVGPU-97 Change-Id: I8900f7635e30578040afa71e0bd470ee835a4748 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1498400 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: disable skedcheck18_l1_config_too_smallSeema Khowala2017-06-13
| | | | | | | | | | | | | SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL disabled Bug 200315442 Change-Id: I6d5c5f2fe6255d480350e01959c3c340579646e2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1499568 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: issue tsg preempt onlySeema Khowala2017-06-13
| | | | | | | | | | | | | | | | | | Preempt type should be set to tsg and id should be set to tsgid in fifo_preempt_r(). Preempt type channel and id set to channel id does not initiate preemption. Bug 200289427 Bug 200292090 Bug 200289491 Change-Id: I2ae96c0b9ca8a88a8405f42775744f0879994887 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1497877 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU init reorg support updateMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | -Updated gv11b HAL, pmu_msgq_tail & pmu_mutex_size to point to gk20a_pmu_msgq_tail() & pwr_pmu_mutex__size_1_v() JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: I8fe271f778fc2d70360f8a508f36d0bfce6b341d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1499701 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU IPC reorg support update Mahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | - prepend PMU IPC func with nvgpu_ by replacing gk20a_ - updated gv11b HAL methods of queue & mutex to point to gk20a HAL methods. JIRA NVGPU-56 Change-Id: Iade9f5613dbd4bc11515e822ddfda3a1787bfa4f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479117 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu specific nvhost APIsDeepak Nibade2017-06-08
| | | | | | | | | | | | | | | | | | | | | | Remove use of linux specifix header files <linux/nvhost.h> and <linux/nvhost_t194.h> and use nvgpu specific header file <nvgpu/nvhost_t19x.h> instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Jira NVGPU-29 Change-Id: I32d59628ca5ab3ece80a10eb5aefa150b1da448b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1494648 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gv11b: ltc reset seqeunce changeseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | Access ltc registers only after bringing ltc out reset. Earlier ltc bought out of reset in fb_reset which is later than accessing ltc registers. GPUT19X-70 Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1495167 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: move cbc init to mmu from ltcseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | | | | Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: gv11b: update init_fs_state gr opsSeema Khowala2017-06-06
| | | | | | | | | | GPUT19X-70 Change-Id: Ifc6c52ac15108d1389fcd732218abf46b6167485 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1486177 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: split vidmem_is_vidmemKonsta Holtta2017-06-06
| | | | | | | | | | | | | Use the new honors_aperture and unified_memory flags instead of vidmem_is_vidmem. Jira NVGPU-86 Change-Id: I5df8b119d30b255fa8d841cec747a187ce3fa588 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1496081 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pass correct parameter to gp10b_ecc_stat_create()Deepak Nibade2017-06-06
| | | | | | | | | | | | | | | | | | | | | | | | | We pass (struct device_attribute *) to gp10b_ecc_stat_create() and gr_gp10b_ecc_stat_create() and then assign a memory allocation to this pointer But since this pointer is local copy to function, static pointer variables are never set in gr_gp10b_create_sysfs() This also results in a resource leak since we never free the storage assigned to local variable Fix this by adding and passing correct parameter (struct device_attribute **) so that the address of the allocation is returned to the caller correctly Bug 200291879 Coverity id : 2567934 Change-Id: I1b1d329265f4d32739abbbe3a4e419a2af62b874 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1495907 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: renamed "struct pmu_gk20a" to "struct nvgpu_pmu"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | JIRA NVGPU-56 Change-Id: I73a375cf2f3d544357fb390491a8d70d12fb8562 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479299 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add chip specific ECC countersDavid Nieto2017-06-04
| | | | | | | | | | | | | Add support for ECC counters for HUB MMU JIRA: GPUT19X-82 Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490825 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: GPC MMU ECC supportDavid Nieto2017-06-04
| | | | | | | | | | | | | Adding support for GPC MMU ECC error handling JIRA: GPUT19X-112 Change-Id: I62083bf2f144ff628ecd8c0aefc8d227a233ff36 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490772 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: L2 cache tag ECC supportDavid Nieto2017-06-04
| | | | | | | | | | | | | Adding support for L2 cache tag ECC error handling JIRA: GPUT19X-112 Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1489029 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: disable czf_bypassseshendra Gadagottu2017-06-02
| | | | | | | | | | | | | | Gv11b ucode is not having support for low latency context-switching. So disable cfz_bypass mode for now. JIRA GPUT19X-116 Change-Id: I814cd254fa3c342c20906805a4b13b52c89d5b1e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1494217 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: payload for syncpt waitseshendra Gadagottu2017-06-02
| | | | | | | | | | | | Program payload for sync point wait command. JIRA GPUT19X-2 Change-Id: I1a8e0176a056aa1c7008761f8b253ec17b5703c2 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1494353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: include <nvgpu/debug.h>Deepak Nibade2017-06-02
| | | | | | | | | | | | | | | Include <nvgpu/debug.h> explicitly wherever the debug operations are used Jira NVGPU-62 Change-Id: I1845e08774b7c211e7fd954937708905f905e069 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1492818 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: use correct parameters for gk20a_debug_dump()Deepak Nibade2017-06-02
| | | | | | | | | | | | | | | | Pass struct gk20a * pointer instead of device pointer to gk20a_debug_dump() API This patch is needed since definition of gk20a_debug_dump() has changed Jira NVGPU-62 Change-Id: I7e67f6b792e575ee72eb6a5b0f7c53e5122a545f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1492113 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gv11b: set only valid soc creditsseshendra Gadagottu2017-06-01
| | | | | | | | | | | | | | | | | | | | | | | Only for following instances, mssnvlink <-> hshub will be interacting in gv11b: NV_ADDRESS_MAP_MSS_NVLINK_1_BASE NV_ADDRESS_MAP_MSS_NVLINK_2_BASE  NV_ADDRESS_MAP_MSS_NVLINK_3_BASE NV_ADDRESS_MAP_MSS_NVLINK_4_BASE   NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub, so don't set those credits. GPUT19X-116 Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1493641 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: No need to set init val for fb & pbdma timeoutSeema Khowala2017-06-01
| | | | | | | | | | | | | | fb_timeout and pbdma_timeout values are already set by h/w to init values. No need to reinitialize. JIRA GPUT19X-22 Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1493458 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update regops whitelistseshendra Gadagottu2017-06-01
| | | | | | | | | | | | | | Update regops whitelist to HW CL#38424879 JIRA GPUT19x-116 Change-Id: I4dd7b54cf04a5e298c191dcb525e6d9d8c591fb0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1492710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fifo ops get_mmu_fault_info set to NULLSeema Khowala2017-05-30
| | | | | | | | | | | | | | mmu fault h/w registers are no longer inside fifo module JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I7d166f0e80cee7c040289b13a053ff2cdb7d8727 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1487327 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init enable_exceptions gr opsSeema Khowala2017-05-30
| | | | | | | | | | | | | | | Enable FE, MEMFMT, DS and GPC exceptions only. Make sure corresponding HWW_ESR are enabled too. JIRA GPUT19X-75 Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1474859 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-17 20:00:23 -0400