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path: root/drivers/gpu/nvgpu/gv11b
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* gpu: nvgpu: Mask an unused HCE_ILLEGAL_OP InterruptVinod G2018-06-14
| | | | | | | | | | | | | | HCE interrupt is not being used in nvgpu platform now, masking the bit from the interrupt register. bug 2082123 Change-Id: I1d53584afebe57b9621c8f4ec395cd1dcd6c7611 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1746850 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add support for FECS VAVaibhav Kachore2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - On t186, ucode expects physical address to be programmed for FECS trace buffer. - On t194, ucode expects GPU VA to be programmed for FECS trace buffer. This patch adds extra support to handle this change for linux native. - Increase the size of FECS trace buffer (as few entries were getting dropped due to overflow of FECS trace buffer.) - This moves FECS trace buffer handling in global context buffer. - This adds extra check for updation of mailbox1 register. (Bug 200417403) EVLR-2077 Change-Id: I7c3324ce9341976a1375e0afe6c53c424a053723 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct calculation of sm_id for .record_sm_error_stateRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle replayable mmu fault during waiting for SM lockdownRichard Zhao2018-06-14
| | | | | | | | | | | | | | outstanding replayable mmu fault will prevent SM from lockdown, so handle the replayable mmu fault while polling lockdown status. Jira EVLR-2643 Bug 200405202 Change-Id: I811f16ef4394a6cc42a5f37a17e426dd749c5652 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741997 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove duplicate NVGPU_SUPPORT_IO_COHERENCE enableAnup Kumar Sah2018-06-14
| | | | | | | | | | | | | | | | | | NVGPU_SUPPORT_IO_COHERENCE is already set in gk20a_probe based on the presence of dma-coherent property of gpu DT so this change removes the redundant enable in gv11b_init_gpu_characteristics VQRM-4044 Change-Id: I8c8d8d485f00aec6fae7a6794fecd855ce3a0004 Signed-off-by: Anup Kumar Sah <asah@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741090 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to allocate/map/commit global context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | Add below new HALs to allocate/map/commit global context buffers gops.gr.alloc_global_ctx_buffers() gops.gr.map_global_ctx_buffers() gops.gr.commit_global_ctx_buffers() Set these HALs for all the supported GPUs We right now re-use below APIs to set these HALs gr_gk20a_alloc_global_ctx_buffers() gr_gk20a_map_global_ctx_buffers() gr_gk20a_commit_global_ctx_buffers() Jira NVGPUT-27 Change-Id: I975a54e8d1716af057f982d543787748d35a256e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743362 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Multiple WPR supportMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | The WPR will be divided into several sub-WPRs, one for each Falcon and one common for sharing between Falcons which bootstrap falcons - Defined & used flag NVGPU_SUPPORT_MULTIPLE_WPR to know M-WPR support. - Added struct lsfm_sub_wpr to hold subWPR header info - Added struct lsf_shared_sub_wpr_header to hold subWPR info & copied to WPR blob after LSF_WPR_HEADER - Set NVGPU_SUPPORT_MULTIPLE_WPR to false for gp106, gv100 & gv11b. - Added methods to support to multiple WPR support & called by checking flag NVGPU_SUPPORT_MULTIPLE_WPR in ucode blob preparation flow. JIRA NVGPUTU10X / NVGPUT-99 Change-Id: I81d0490158390e79b6841374158805f7a84ee6cb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Handle all SM errorsVinod G2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | Add the missing register bits to identify the SM errors. Except for mmu_nack error, all other errors are handled using a single function. That function sets the error notifier with GR_EXCEPTION, clears interrupt and triggers recovery process. bug 200402677 JIRA NVGPU-573 Change-Id: Icfaff1f20f1f35adb4cd35ce288ce694845aed3c Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730963 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Combine variants of init_mm_setup_hwTerje Bergstrom2018-06-14
| | | | | | | | | | | | | | gp10b and gk20a variants of init_mm_setup_hw were essentially the same. Delete the gp10b version and use gk20a variant instead. gv11b variant now also inherits gk20a variant. JIRA NVGPU-588 Change-Id: I842516a1c0be68562ad0ece6e1837a1416d24957 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730897 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement bus HAL for bar2 bindTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Separate timer from busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting of BAR0_WINDOW to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to common code so that pramin_gk20a.[ch] can be deleted. JIRA NVGPU-588 Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730890 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting priv interrupt to priv_ringTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add g->fifo_eng_timeout_usThomas Fleury2018-06-14
| | | | | | | | | | | | | | Add g->fifo_eng_timeout_us to define engine timeout in microseconds. It is initialized with GRFIFO_TIMEOUT_CHECK_PERIOD_US. In RM server case, it can be overriden with value defined in device tree. Jira EVLR-2674 Change-Id: I69ac2ce779fe575566c8ba48e8cd2d0e6b2d93cf Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1728391 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b/gv100: add SHADER_CUT_COLLECTOR compute classSeema Khowala2018-05-30
| | | | | | | | | | | | | | | | | | | | Support NVC3C0_SET_SHADER_CUT_COLLECTOR s/w method for compute class. This is needed to enable/disable SHADER_CUT_COLLECTOR_STATE. Bug 2108381 Bug 2099681 Change-Id: I228dcc55b6df605aeeee094f872157023e3c783c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730634 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Wei Sun <wsun@nvidia.com> Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix include path for clockgating headersVinod G2018-05-29
| | | | | | | | | | | | Removed the reference for $NVGPU/drivers/gpu/nvgpu/common from Makefile and fixed the include path for the clockgating headers in HAL files. Change-Id: I34c179866d28c932501b38184ec18d20dce81480 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730759 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: move to use gops.fifo.check_tsg_ctxsw_timeoutRichard Zhao2018-05-25
| | | | | | | | | | | | | Fixing RM server crash when handles ctxsw timeout. RM server needs to call its own HAL of .check_tsg_ctxsw_timeout. Jira EVLR-2691 Change-Id: Ibbc09cbcda39d44dc2a721c9b270d065e13fa9e2 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729900 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move bus HAL to commonTerje Bergstrom2018-05-25
| | | | | | | | | | | Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to enable/disable hub interruptsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export hub intr handling APIsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | | | | | | | Export below APIs in fb_gv11b.h gv11b_fb_handle_dropped_mmu_fault() gv11b_fb_handle_other_fault_notify() gv11b_fb_handle_mmu_nonreplay_replay_fault() gv11b_fb_handle_nonreplay_fault_overflow() gv11b_fb_handle_replay_fault_overflow() gv11b_handle_l2tlb_ecc_isr() gv11b_handle_hubtlb_ecc_isr() gv11b_handle_fillunit_ecc_isr() Jira NVGPUT-44 Change-Id: Ib50e3f3c2f698d486ffe718ebf4a651ccfe8cd93 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725976 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-21
| | | | | | | | | | | | | | | | As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLISTDavid Li2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist, and optionally check host and FECS status to preempt pending load of context not belonging to the calling channel on GR engine during context switch. This should be called immediately after a submit to decrease worst case submit to start latency for high interleave channel. There is less than 0.002% chance that the ioctl blocks up to couple miliseconds due to race condition of FECS status changing while being read. For GV11B it will always preempt pending load of unwanted context since there is no chance that ioctl blocks due to race condition. Also fix bug with host reschedule for multiple runlists which needs to write both runlist registers. Bug 1987640 Bug 1924808 Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1549050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: runlist_lock released before preempt timeout recoverySeema Khowala2018-05-17
| | | | | | | | | | | | | | | | | Release runlist_lock and then initiate recovery if preempt timed out. Also do not issue preempt if ch, tsg or runlist id is invalid. tsgid could be invalid for below call trace gk20a_prepare_poweroff->gk20a_channel_suspend-> *_fifo_preempt_channel->*_fifo_preempt_tsg Bug 2065990 Bug 2043838 Change-Id: Ia1e3c134f06743e1258254a4a6f7256831706185 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662656 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement new host semaphore methods for VoltaDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Semaphore methods currently being used in Volta are deprecated for future chips And on Volta we support both old and new methods So replace old methods by new methods on Volta itself so that new methods get tested on silicon Implement below HALs for Volta with new semaphore methods gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Also use new methods in these APIs gv11b_fifo_add_syncpt_wait_cmd() gv11b_fifo_add_syncpt_incr_cmd() And change corresponding APIs to reflect correct size of command buffer gv11b_fifo_get_syncpt_wait_cmd_size() gv11b_fifo_get_syncpt_incr_cmd_size() Jira NVGPUT-16 Change-Id: Ia3a37cd0560ddb54761dfea9bd28c4384cd8a11c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704518 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to insert semaphore commandsDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | Add below new HALs gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/ release sequence and set it to gops.fifo.add_sema_cmd() Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size() to return respective command buffer sizes Jira NVGPUT-16 Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704490 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix build errors on qnx for thermRichard Zhao2018-05-15
| | | | | | | | | | | | | | | | | | | - include therm header file in source file - remove unreferenced function JIRA VQRM-2343 Change-Id: Ibfeaf1e431631fa2b9a8e8f1bf044c17edc018c5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706201 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Tested-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel <nipatel@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove access to mc_enable_pb_r()Deepak Nibade2018-05-10
| | | | | | | | | | | | | We don't need to configure mc_enable_pb_r() register in any of the supported chips, so remove access to this register Jira NVGPUT-52 Change-Id: I8a7a524367ce7953f926143242c6d63bc8fd5ed1 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1711245 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to handle nonstall interruptsDeepak Nibade2018-05-07
| | | | | | | | | | | | | | | | | | | | | Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts We already handle nonstall interrupts in nvgpu_intr_nonstall() But this API is completely in linux specific code Separate out os-independent code to handle nonstall interrupts in new API mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all existing chips Call this HAL from nvgpu_intr_nonstall() Jira NVGPUT-8 Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1706589 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fixups for tmake buildAlex Waterman2018-05-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly just including necessary includes to make sure that global function declarations actually match their implementations. Also work around pointer munging warning: /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg': /build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing] (*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE); Work around this warning by simply moving the type punning. This code is certainly dangerous - it assumes the endianness of the header data is the same as the machine this code is running on. Apparently it works, though, so this ignores the warning. JIRA NVGPU-525 Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1692454 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to mmu fault descriptors.Vinod G2018-05-04
| | | | | | | | | | | | | | | mmu fault information for client and gpc differ on various chip. Add separate table for each chip based on that change and add hal functions to access those descriptors. bug 2050564 Change-Id: If15a4757762569d60d4ce1a6a47b8c9a93c11cb0 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704105 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add sw method for SHADER_CUT_COLLECTORseshendra Gadagottu2018-05-04
| | | | | | | | | | | | | | | | | | Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR to enable/disable SHADER_CUT_COLLECTOR_STATE. Added support for this sw method in gv11b and gv100. Bug 2108381 Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703662 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add rc_type i/p param to gk20a_fifo_recoverSeema Khowala2018-05-04
| | | | | | | | | | | | | | | | | | | | | Add below rc_types to be passed to gk20a_fifo_recover MMU_FAULT PBDMA_FAULT GR_FAULT PREEMPT_TIMEOUT CTXSW_TIMEOUT RUNLIST_UPDATE_TIMEOUT FORCE_RESET SCHED_ERR This is nice to have to know what triggered recovery. Bug 2065990 Change-Id: I202268c5f237be2180b438e8ba027fce684967b6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662619 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename mutex to runlist_lockSeema Khowala2018-05-04
| | | | | | | | | | | | | | Rename mutex to runlist_lock in fifo_runlist_info_gk20a struct. This is good to have for code readability. Bug 2065990 Bug 2043838 Change-Id: I716685e3fad538458181d2a9fe592410401862b9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1662587 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox sizeSeema Khowala2018-05-01
| | | | | | | | | | | | | | fecs_ctxsw_mailbox_size varies per chip. Use hal to get the size. Also dump fecs_ctxsw_status_1 to help debug Bug 2093809 Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698026 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix priv error for slcg regSeema Khowala2018-04-27
| | | | | | | | | | | | | | Bug 2102373 Change-Id: I13a5faa18cf26233eb04ac08d2b8755aeb56ae4b Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696890 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to update doorbellDeepak Nibade2018-04-27
| | | | | | | | | | | | | | | | | | | | Add new HAL gops.fifo.ring_channel_doorbell() to update channel doorbell register and to trigger a runlist scan Set existing API gv11b_ring_channel_doorbell() to this HAL for all volta chips Jira NVGPUT-18 Change-Id: I9d5e84cf5aa7b763363d84befe169efda00a0932 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702114 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move mss nvlink credit init to os specific codeRichard Zhao2018-04-25
| | | | | | | | | | | | | | | | | | The code uses ioremap, readl_relaxed/writel_relaxed, which only exists on linux. So move them to linux folder. Also fix build errors on qnx. Jira VQRM-2344 Change-Id: Ide1176d0bf954a804187aa842a6bbfdecbdb0286 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698973 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-04-25
| | | | | | | | | | | | | | | | | | Only for gv11b A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I027f923b63b24bbbc054a7d9a377d757994a07ad Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700981 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to submit and wait for runlistDeepak Nibade2018-04-24
| | | | | | | | | | | | | | | | | | | | | | | | Add below two new HALs gops.fifo.runlist_hw_submit() to submit a new runlist to hardware gops.fifo.runlist_wait_pending() to wait until runlist write is successful Set existing API gk20a_fifo_runlist_wait_pending() to gops.fifo.runlist_wait_pending HAL Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w and set it to gops.fifo.runlist_hw_submit HAL Jira NVGPUT-20 Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700548 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: post dbg session header file changePrateek Sethi2018-04-24
| | | | | | | | | | | | | | | | | | | | Need to include bug.h and dbg_gpu_gv11b.h to fix compilation issue at QNX. These changes are required as part of debug session unification. Jira VQRM-2363 Change-Id: I543dab8be16ef6eb321c31f2f262e4dbdeb7dd6a Signed-off-by: Prateek Sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699079 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export gv11b fifo APIsDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | | | | Export below APIs from fifo_gv11b.h gv11b_fifo_init_ramfc_eng_method_buffer() gv11b_userd_writeback_config() Also move #define PBDMA_SUBDEVICE_ID to header file Jira NVGPUT-19 Change-Id: I5e3abf02acfe014e39550f236d60d8991a75b4ef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699315 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to set ppriv timeoutsDeepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | | Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific ppriv timeouts Set this HAL for all supported GPUs for now Jira NVGPUT-35 Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699314 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove use of pb_header_priv_user()Deepak Nibade2018-04-22
| | | | | | | | | | | | | | | | | H/W field NV_PPBDMA_PB_HEADER_PRIV is obsolete in Volta and has no effect Hence remove use of pb_header_priv_user() from channel_gv11b_setup_ramfc() Jira NVGPUT-31 Change-Id: I0bb08c5d5a26218bb057e19983044dac5238142f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1699313 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: add hal op for gr set error notifier"Richard Zhao2018-04-19
| | | | | | | | | | | | | | | This reverts commit d6c6c6c483478654b34685b9e13ed160bad49a1c. RM server has moved to gops.fifo.set_error_notifier. gops.gr.set_error_notifier is not needed anymore. Jira VQRM-3058 Change-Id: I0fe7f914778ce66701a699aece2b36a5cd8079da Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1679708 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: consider floorswept FBPA for getting unicast listDeepak Nibade2018-04-16
| | | | | | | | | | | | | | | | | | | | | | | | In gr_gv11b/gk20a_create_priv_addr_table() we do not consider floorswept FBPAs and just calculate the unicast list assuming all FBPAs are present This generates incorrect list of unicast addresses Fix this introducing new HAL ops.gr.split_fbpa_broadcast_addr Set gr_gv100_get_active_fpba_mask() for GV100 Set gr_gk20a_split_fbpa_broadcast_addr() for rest of the chips gr_gv100_get_active_fpba_mask() will first get active FPBA mask and generate unicast list only for active FBPAs Bug 200398811 Jira NVGPU-556 Change-Id: Idd11d6e7ad7b6836525fe41509aeccf52038321f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694444 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix gpc/tpc index for SMPC broadcast conversionDeepak Nibade2018-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | In gv11b_gr_egpc_etpc_priv_addr_table(), we call gv11b_gr_update_priv_addr_table_smpc() to convert SMPC broadcast address into list of unicast addresses But before calling gv11b_gr_update_priv_addr_table_smpc() we sometimes incorrectly set gpc_num/tpc_num to zero and that leads to generating incorrect list of unicast addresses Remove this incorrect initialization of gpc_num/tpc_num Also update gv11b_gr_egpc_etpc_priv_addr_table() to receive tpc_num along with gpc_num Bug 2099717 Jira NVGPU-580 Change-Id: Idd4e5f78dbe6ca1800efae93c66355d06417d1f2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1691373 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-12 15:59:37 -0400