| Commit message (Collapse) | Author | Age |
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Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.
Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Implement gv11b platform specific rail gating functions
by calling relevant powergate and unpowergate functions
and linux clock frmework functions:
gv11b_tegra_is_railgated
gv11b_tegra_railgate
gv11b_tegra_unrailgate
These calls will take care of hot reset sequence
required for gpu powergate and gpu unpowergate.
Bug 200269361
Bug 200273571
Change-Id: Ib1825e4324d51fc508b3b5dc9e5e2fdb252eeff4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589509
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix #includes in all the files to include platform_gk20a.h file with
correct path
NVGPU-316
Change-Id: Icb26d3c75076b8fdc8da992f751e1cfea22996be
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589939
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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API gr_gv11b_create_sysfs() and GR HAL create_gr_sysfs() right now receive
linux specific struct device
But since this function is called from/declared in common code, we need to
remove linux dependency from it
Hence update the API and GR HAL to receive struct gk20a pointer instead
of device pointer
Jira NVGPU-259
Change-Id: I65d717ad9f263f0397f8efa5761c64e55c7846eb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1588465
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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For pre-silicon platforms, clock gating
should be skipped as it is not supported.
Added new flags "can_"x"lcg" to check platform
capability before programming SLCG,BLCG and ELCG.
Bug 200314250
Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566251
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Change license of OS independent source code files to MIT.
JIRA NVGPU-218
Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567804
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Stop defining per-platform default big page size. It's defined via
HAL and inherited from gp10b.
JIRA NVGPU-38
Change-Id: If5eedd5d351d5504bdf87489d1aa091d430c43ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1508069
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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JIRA GPUT19X-2
Change-Id: If69567af3f6de6cd65429086578715fb4d6dfeb5
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1323440
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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tegra/linux path was created to separate Tegra kernel specific
dependencies from common Linux specific dependencies. The split has
not really worked, so merge tegra/linux to common/linux.
JIRA NVGPU-38
Change-Id: I9efe078bfa5dfbef49408db9d8a3738dfda8bd1d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505169
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Remove use of linux specifix header files
<linux/nvhost.h> and <linux/nvhost_t194.h>
and use nvgpu specific header file
<nvgpu/nvhost_t19x.h> instead
This is needed to remove all Linux dependencies
from nvgpu driver
Replace all nvhost_*() calls by
nvgpu_nvhost_*() calls from new nvgpu library
Jira NVGPU-29
Change-Id: I32d59628ca5ab3ece80a10eb5aefa150b1da448b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1494648
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Use the new honors_aperture and unified_memory flags instead of
vidmem_is_vidmem.
Jira NVGPU-86
Change-Id: I5df8b119d30b255fa8d841cec747a187ce3fa588
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1496081
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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We pass (struct device_attribute *) to gp10b_ecc_stat_create()
and gr_gp10b_ecc_stat_create() and then assign a memory
allocation to this pointer
But since this pointer is local copy to function, static
pointer variables are never set in gr_gp10b_create_sysfs()
This also results in a resource leak since we never free
the storage assigned to local variable
Fix this by adding and passing correct parameter
(struct device_attribute **) so that the address of the
allocation is returned to the caller correctly
Bug 200291879
Coverity id : 2567934
Change-Id: I1b1d329265f4d32739abbbe3a4e419a2af62b874
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1495907
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for ECC counters for HUB MMU
JIRA: GPUT19X-82
Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1490825
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Adding support for GPC MMU ECC error handling
JIRA: GPUT19X-112
Change-Id: I62083bf2f144ff628ecd8c0aefc8d227a233ff36
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1490772
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Adding support for L2 cache tag ECC error handling
JIRA: GPUT19X-112
Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1489029
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In t19x, host1x supports sync point through memory mapped
shim layer. So sync-point operations implemented through
semphore methods signaling to this sync-point shim layer.
Added relevant hal functions for this in fifo hal.
JIRA GPUT19X-2
Change-Id: Ia514637d046ba093f4e5afa6cbd06673672fd189
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258235
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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(1) Re-arrange the structure for ecc counters reporting so multiple
units can be managed
(2) Add counters and handling for additional GPC counters
JIRA: GPUT19X-84
Change-Id: I74fd474d7daf7590fc7f7ddc9837bb692512d208
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485277
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add handling of GCC L1.5 parity exception.
JIRA GPUT19X-86
Change-Id: Ie83fc306d3dff79b0ddaf2616dcf0ff71fccd4ca
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1485834
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache
Volta Resiliency Id - Volta-634
JIRA GPUT19X-113
JIRA GPUT19X-99
Bug 1807553
Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This CL covers the following parity support (uncorrected error),
1) SM's LRF
2) SM's CBU
Volta Resiliency Id - Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-110
Bug 1775457
Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1481791
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This CL covers the following parity support (corrected + uncorrected),
1) SM's L1 tags
2) SM's S2R's pixel PRF buffer
3) SM's L1 D-cache miss latency FIFOs
Volta Resiliency Id - Volta-720, Volta-721, Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-104
JIRA GPUT19X-100
JIRA GPUT19X-103
Bug 1825948
Bug 1825962
Bug 1775457
Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1478881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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platform_tegra.h got moved under tegra/linux, so fix the path.
JIRA NVGPU-16
Change-Id: I18d4e35e4ea781b6d67f7999e4470862752aafaf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463537
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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This reverts commit 90d029fd28c25904bb84f929f1a65075a8d9b6e4.
Bug 200305653
Change-Id: I2baa4b286e14ce57e68ab1e9cc15630ee24f5bc9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1475515
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fixed following sparse warning by including relevant header:
$TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c:82:23:
warning: symbol 't19x_gpu_tegra_platform' was not declared. Should it be static?
Bug 200299572
Change-Id: Ibf7b69da9b76e72d610571135bd412c865b69a5f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1474940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use the new clk HAL to request clock rate instead of direct calls
to Clock Framework. This cuts one direct dependency to Linux APIs.
Also change the HAL to not clear clk ops after they've been
initialized.
JIRA NVGPU-16
Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463536
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Do not depend on bypass_smmu to set disable_bigpage
Bug 1805409
Change-Id: Ie602e3567162896acbc6a2da5f7f2db5cfb8021f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1465071
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All GPUs have a copy engine. So delete the flag has_ce, because
it's always true.
JIRA NVGPU-16
Change-Id: I6daa77ff70ccc0195352109916cb98b43a2109de
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1325357
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Drop one #include, its contents are not used.
Bug 1853519
Change-Id: I51480b1d75b36c993af3a5005ee9b7fc6dee8a54
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1326127
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The calls to nvhost_{register,unregister}_client_domain don't do
anything, so remove the platform device's late_probe and remove ops that
serve no other purpose than calling those empty functions. Remove also
the corresponding #includes which are now unused.
Bug 1853519
Change-Id: I67149d1575be5b3cacc60e6c28e6f2debfabf71c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1326126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Init below fields in t19x_gpu_tegra_platform
-reset_assert = gp10b_tegra_reset_assert
-reset_deassert = gp10b_tegra_reset_deassert
JIRA GV11B-34
Change-Id: I69cff5621d7fa7de830567f4cce87f79934809e2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1296909
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gp10b_tegra_get_clocks called from gv11b_tegra_probe.
Also gv11b_tegra_probe is called from nvgpu_probe via function
ptr platform->probe
JIRA GV11B-34
Change-Id: I782286e191eef84ce41bc65440fbe5ae00995af3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1296840
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The driver file includes <linux/tegra-powergate.h> but does
not use anything from this header.
Remove this unnecessarily inclusion of header file.
bug 200257351
Change-Id: Ibbc3c382c31a8c566ed4018fd36d1ffed08bf29e
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1300556
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Similar HW header update as has been done for all the other chips.
HW header files are located under:
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/
And can be included like so:
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
Bug 1799159
Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gpu is completely out from host1x block and
no need to create device nodes under host1x.
Bug 1735760
Change-Id: I2df861b07b38ce6931a86a928184ad164095948a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1181063
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added control flag for nvgpu infra to allow kernel to create privileged
CE channels for page migration and clearing support between sysmem
and videmem.
JIRA DNVGPU-53
Change-Id: I2d1faf034e194b7a850ac33aec4f6c315c7e552b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1173093
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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For gv11b, set platform data for soc memory aperture type
to sysmem instead of vidmem.
Bug 1749338
Change-Id: I6632e79e3ca68c437e5b04f6865f8f0b6f2943ce
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1129169
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Bug 1735757
Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1122123
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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