summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
Commit message (Collapse)AuthorAge
* gpu: nvgpu: gv11b: skip mmu fault buf alloc after resumeSeema Khowala2018-01-24
| | | | | | | | | | | | | Skip allocating memory if required s/w set up for mmu fault buffers is already done. Bug 2045228 Change-Id: Ib88e8dd4f54b3f0faf7dc9edf091ec285220f7b5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640516 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove fault_buf_status arrayAlex Waterman2018-01-24
| | | | | | | | | | | | Now that we have a consistent way to check if a mem allocation is valid this array is not necessary. The code can simply check the validity of the nvgpu_mem. Change-Id: I6aaf563ddc314cf86a2c2b98f7eb75fa7a9a1ad9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1641637 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove extranneous linux include in mm_gv11b.cSourab Gupta2018-01-24
| | | | | | | | | | | The patch removes the extranneous linux include in the file mm_gv11b.c, which is not required. Change-Id: I6d5a5d27ec9120ad7784348ba81f9e5d0c320c19 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643293 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fold T19x code back to main code pathsTerje Bergstrom2018-01-23
| | | | | | | | | | | | | Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cleanup generic MM codeAlex Waterman2017-10-24
| | | | | | | | | | | | | | t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv10x: alloc fault buffer in sysmemDavid Nieto2017-10-23
| | | | | | | | | | | | | | | With coherency issues solved, it is no longer needed to allocate the fault buffer in vidmem as a workaround. JIRA: NVGPUGV100-36 Change-Id: I1c83e9bac61f27b75f38fce963899485afeed009 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582769 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix GV100 hal definitionsDavid Nieto2017-10-10
| | | | | | | | | | | | | | | | | | | | | These changes allow GV100 to init the basic HALs to pass nvgpu_submit_twod (1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency issues (2) Properly enable FB (3) Fan control requires the execution of the pre-os FW, without it the SKU201 is extremely noisy JIRA: NVGPUGV100-9 Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539926 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Change license for common files to MITTerje Bergstrom2017-09-25
| | | | | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Reorg mm HAL initializationSunny He2017-08-14
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: Reorg mm HAL init"Sunny He2017-08-11
| | | | | | | | | | | This reverts commit 96615351ad11a186f5869e56acb3c1948ab7b7cc, which conflicts with gv100 changes. Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537667 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* gpu: nvgpu: gv11b: Reorg mm HAL initSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove mm.get_iova_addrAlex Waterman2017-08-04
| | | | | | | | | | | | Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix L3 alloc bitDeepak Nibade2017-08-02
| | | | | | | | | | | | | | | | | | Last minute rebase of commit afa31cdd8cc6bb04faeed30b2cc30f5e6be888b5 on top of reworked memory infrastucture introduced a bug where we actually need to set BIT(36) in physical address but we ended up ORing the address by "36" Fix this by by adding correct value BIT(36) instead of 36 Jira GPUT19X-10 Bug 200279508 Change-Id: Ib587849c75f57dda5ad802b8389b7563b8b690ed Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1529511 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: check bar2 bind_statusSeema Khowala2017-07-11
| | | | | | | | | | | | | | This is needed as BAR1 support is removed and there is no way to know if gpu successfully accessed memory. JIRA GPUT19X-115 Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1515813 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: add mmu fault handlingSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: set up for enabling/handling hub intrSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add support for L3 cache allocation of buffersDeepak Nibade2017-07-07
| | | | | | | | | | | | | | | | | | | | Add gv11b implementation of gpu_phys_addr() that checks the t19x GMMU attributes struct to determine if L3 allocation should be enabled. If L3 alloc is enabled then a special physical address bit is set. Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct nvgpu_as_map_buffer_ex_args so that User space can add a hint to allocate buffer in L3 cache Jira GPUT19X-10 Bug 200279508 Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master/r/1512602 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: fb_flush before/after l2_flushseshendra Gadagottu2017-06-20
| | | | | | | | | | | | | | | | | | | | After enabling l2 write back in gv11b, for committing all dirty data to sysmem correctly: Added one fb_flush before l2_flush to commit dirty hshub data to l2/sysmem. Added one more fb_flush after l2_flush, to commit any new dirty data on hshub to sysmem. This done by implementing gv11b specific l2_flush function. Bug 1937331 Change-Id: Ie30edb12c98c4021783c88750bb4c4ca62e4a7ca Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1503385 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename mem_desc to nvgpu_memAlex Waterman2017-04-06
| | | | | | | | | | | | | $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init mm ops for mmu_fault_pendingSeema Khowala2017-03-22
| | | | | | | | | | | | mmu fault reporting is moved from fifo* to fb* and gmmu* hw registers. JIRA GPUT19X-7 Change-Id: If2040ab661229c2e734042f2eec1592030615fee Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1315203 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: abstract away dma alloc attrsKonsta Holtta2017-03-21
| | | | | | | | | | | | | | Don't use gk20a_gmmu_free_attr because the attrs are embedded in struct mem_desc now. Bug 1853519 Change-Id: Iaa4309d4c2cd334346e09c4fbf15ce826f2ff640 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321314 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: implement mm_setup_hwseshendra Gadagottu2016-11-29
| | | | | | | | | | | | | Reuse gk20a_mm_setup_hw for gv11b. JIRA GV11B-21 Change-Id: I5141dbb8088799a8bd5df55469bc371b63497e96 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254939 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: chip specific init_inst_blockseshendra Gadagottu2016-11-21
| | | | | | | | | | | | | Remove va limits for inst block in gv11b. JIRA GV11B-21 Change-Id: I5338e2d64b3bbebeb5e309d63db3e8360ae05723 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254880 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2016-10-17
| | | | | | | | | | | | | | | | Fix following sparse warning my making funtion as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:23:6: warning: symbol 'gv11b_mm_is_bar1_supported' was not declared. Should it be static? Bug 200088648 Change-Id: I4af7ed1ae112813887a14a11b8fcea0b72c90e39 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1236689 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sysmem userd supportseshendra Gadagottu2016-10-11
| | | | | | | | | | | | | | | | | | | For gv11b, userd is allocated from sysmem. Updated gp_get and gp_put functions to read or write from sysmem instead of bar1 memory. In gv11b, after updating gp_put, it is required to notify pending work to host through channel doorbell. JIRA GV11B-1 Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1226613 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 13:32:00 -0400