| Commit message (Collapse) | Author | Age |
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Access ltc registers only after bringing ltc
out reset. Earlier ltc bought out of reset in
fb_reset which is later than accessing ltc registers.
GPUT19X-70
Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1495167
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added cbc_init in fb and removed cbc_init from ltc.
Also avoid writing into read only registers in ltc.
GPUT19X-70
GPUT19X-116
Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1484525
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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Adding support for L2 cache tag ECC error handling
JIRA: GPUT19X-112
Change-Id: I9a8ebefe97814b341f57a024dfb126013adaac1c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1489029
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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nvgpu_log/info/warn/err() internally add a \n to the end of the message.
Hence, callers should not include a \n at the end of the message. Doing
so results in duplicate \n being printed, which ends up creating empty
log messages. Remove the duplicate \n from all messages.
Bug 1928311
Change-Id: I21c141934a125e0cc0cead9fb19fa6502235cf06
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: http://git-master/r/1487233
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Functions that are not declared in header files are made static
Bug 200299572
Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1471538
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer.
Convert the last remaining user of old macros to new ones.
JIRA NVGPU-16
Change-Id: Ib665cfb395fe46ac988ed14d67adef885098e524
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1462968
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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There is no peermem access for gv11b nvlink.
So no need to enable peermem access through l2.
Implemented gv11b specific ltc_cbc_fix_config
function to read correct num_active_ltcs.
JIRA GV11B-71
Change-Id: I348ce3bbf42e864341494e386b6f33478badb3a8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1315148
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implemented gv11b specific l2 state init and Configured
ltc_ltcs_ltss_cbc_num_active_ltcs_r with following info:
- cbc_num_active_ltcs is read only for gv11b, so did not
write any data to that field.
- enforced serilized access to l2 from sysmem and peermem.
- nvlink connected peer trafic sent through l2
JIRA GV11B-71
Change-Id: I63d9ee3f0a6da62e672a34e207f1f5214b6ed1b4
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1312831
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Similar HW header update as has been done for all the other chips.
HW header files are located under:
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/
And can be included like so:
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
Bug 1799159
Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1284433
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.
Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2
JIRA GV11B-9
Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.
Bug 1735757
Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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