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path: root/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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* gpu: nvgpu: add support for ACB SLCG on gv11bprsethi2020-10-27
| | | | | | | | | | | | | | | | | | | | | | Register list for ACB SLCG is auto generated with scripts. Add HAL operations to enable/disable ACB clock gating. Cherry-pick/manually port from dev-main Bug 200647909 Change-Id: I4be4c14cc072fcccd91031a5a40321f5ff11f549 Signed-off-by: Prateek sethi <prsethi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420355 (cherry picked from commit c7c04d3a28c2eb0edc8e015dd0130fa50d3496c7) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434464 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Phoenix Jung <pjung@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: wait ACK for FECS watchdog timeoutDeepak Nibade2020-07-14
| | | | | | | | | | | | | | | | | | | On Volta, nvgpu needs to wait for explicit ACK from CTXSW while setting FECS watchdog timeoout This is manual port of the fixes 4d7e5026e38528b88a4a168eca9a8b180475b368 and ad89436b03428a42e43042b6a849c15843fdebc4 on dev-main since clean cherry-pick is not possible due to huge file and structure differences. Bug 200603566 Change-Id: Icba69998ab45eee5fdf2a29e1ac1067589301be6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2371708 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: initialize masks for the perfmon counters 3David Ung2020-05-22
| | | | | | | | | | | | | | | | | | | Initialize the perfmon counters #3 masks to be same values as ELPG. Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030, but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0. Bug 2833620 Change-Id: I3a424345aec6176a97dd20fb2c68a6e2faf955ad Signed-off-by: David Ung <davidu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: fix tsg_unbind in recovery casePeter Daifuku2020-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When unbinding a channel from a tsg when virtual, vgpu_tsg_unbind_channel would return an error if unbinding the channel on the guest side failed, and did so before notifying the RM server of the unbind. Later on in the recovery process, the guest OS would remove the channel from the TSG's list, but this would leave the RM server with an out-of-date channel list. Fix this by making the tsg_unbind_channel HAL optional and implemented only for vgpu: the vgpu version now just notifies the RM server so that it can clean up its version of the TSG; if vgpu, always call the tsg_unbind_channel HAL whether or not the local unbind succeeded. Minimal port from dev-main of https://git-master.nvidia.com/r/c/linux-nvgpu/+/2084029 Bug 2766920 Bug 200587845 Change-Id: I75bddf3a28ac20bf4fb7510ff64097a32c7eec3f Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287774 (cherry picked from commit 471c72c1efcc4fe6d547f556edf7773827fd2674) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289928 Reviewed-by: Thomas Steinle <tsteinle@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: set FB/HSMMU debug modeThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE Bug 2515097 Bug 2713590 Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115785 (cherry picked from commit 8057514a9f7fc5f175e2e0571dfa91d78ebb6410) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable MMU_DEBUG_MODE for gv11bThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl for gv11b. Bug 2515097 Bug 2713590 Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115019 (cherry picked from commit 3f9ea7dfd854d748c3d0fae52e2981bae1c8e650) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208768 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctlThomas Fleury2020-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add platform atomic supportVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | Add new variable in nvgpu_as_map_buffer_ex_args for app to specify the platform atomic support for the page. When platform atomic attribute flag is set, pte memory aperture is set to be coherent type. renamed nvgpu_aperture_mask_coh -> nvgpu_aperture_mask_raw function. bug 200580236 Change-Id: I18266724dafdc8dfd96a0711f23cf08e23682afc Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2012679 (cherry picked from commit 9e0a9004b71f92b7713fd3b30141b0d9d4cfa2c6) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274914 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: set CE prod valuesDeepak Nibade2019-11-04
| | | | | | | | | | | | | | | | | | | | | Add g->ops.ce.init_prod_values() hal for gv11b to initialize PROD values of CE unit Bug 2526212 Chery-pick/manual port from dev-main Change-Id: I8e516b292622e09c537feb7830392648116baa7c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150874 (cherry picked from commit 0e6a305c6af3ea6d9a0cad7b4071f68028a1aebe) Reviewed-on: https://git-master.nvidia.com/r/2224709 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add clock gating support for HSHUBDeepak Nibade2019-11-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add BLCG and SLCG clock gating support for HSHUB unit on gv11b Register list for BLCG and SLCG is auto generated with scripts. Add HAL operations to enable/disable HSHUB clock gating Re-generate gv11b reglist so that all the manually commented registers are automatically deleted. Some of the unicast registers are also deleted. We already have corresponding broadcast registers present. Cherry-pick/manually port from dev-main Bug 2526212 Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150199 (cherry picked from commit e34b6f76d38ad5641c1ed7c3a4b36752d9dd4750) Reviewed-on: https://git-master.nvidia.com/r/2224708 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Luis Dib <ldib@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Enabling/disabling FECS trace supportseshendra2019-09-06
| | | | | | | | | | | | | | | | | | | - To enable FECS trace support, nvgpu should set the MSB of the read pointer (MAILBOX1). - The ucode will check if the feature is enabled/disabled before writing a record into the circular buffer. If the feature is disabled, it will not write the record. - If the feature is enabled and the buffer is not allocated, HW will throw a page fault error. Bug 2459186 Bug 200542611 Change-Id: I6f181643737d1cf1bda02077eaa714a3f4ef3d8c Signed-off-by: seshendra <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2189250 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add usermode_base HALKonsta Holtta2019-08-15
| | | | | | | | | | | | | | | | | | | | Add a HAL function pointer to fifo to for reading the usermode_cfg0 register and implement it for gv11b. Bug 200145225 Bug 200541476 Change-Id: I5f77b15d3b502d9370b1f14129314eaf51a9d7d1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1811839 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit fddb2969240652e1a56089b249684b55430d45c5 in dev-main) Reviewed-on: https://git-master.nvidia.com/r/2170004 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use TPC_PG_MASK to powergate the TPCDivya Singhatwaria2019-08-02
| | | | | | | | | | | | | | | | | | | | | | | - In GV11B, read fuse_status_opt_tpc_gpc register to read which TPCs are floorswept. - The driver will also read sysfs node: tpc_pg_mask - Based on these two values "can_tpc_powergate" will be set to true or false and mask will be used to write to fuse_ctrl_opt_tpc_gpc register to powergate the TPC. - can_tpc_powergate = true indicates that the mask value sent from userspace is valid and can be used to power gate the desired TPC - can_tpc_powergate = false indicates that the mask value sent from userspace is not valid and cannot be used to power gate the desired TPC. Bug 200532639 Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2159219 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fecs ctxsw trace for gm20bDebarshi Dutta2019-05-14
| | | | | | | | | | | | | | | | | | Register gk20a non-arch-specific functions for gm20b gpu_ops.fecs_trace, Register nvgpu_os_linux_ops.fecs_trace.init_debugfs gp10b_fecs_trace_flush is now replaced by gm20b_fecs_trace_flush in fecs_trace_gm20b.* and the fecs_trace_gp10b.* files are removed. Bug 2052906 Change-Id: I245c91ae8e6015b87bafeb3ec023b98fe4c57501 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2115247 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add hal to mask/unmask intr during teardownSeema Khowala2019-05-02
| | | | | | | | | | | | | | | | | | | | | | ctxsw timeout error prevents recovery as it can get triggered periodically. Disable ctxsw timeout interrupt to allow recovery. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I47470e13968d8b26cdaf519b62fd510bc7ea05d9 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2019645 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry picked from commit 68c13e2f0447118d7391807c9b9269749d09a4ec in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2024899 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: using pmu counters for load estimatePeng Liu2019-04-01
| | | | | | | | | | | | | | | | | | | | | | | | | | PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu <pengliu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian <atian@nvidia.com> Tested-by: Aaron Tian <atian@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Tested-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL-ify pmm type broadcast valuesmatthewb2018-10-11
| | | | | | | | | | | | | | | | | | | | The PMM type-specific broadcast->unicast expansion calculation was using incorrect values. This caused the invalid register accesses to be generated. This change HAL-ifies the values, so that the expansion will be performed correctly. Bug 200454109 Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564 Signed-off-by: Matthew Braun <matthewb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921717 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove VPR HALs from dGPUsDeepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers. Split this into two different HALs gops.fb.dump_vpr_info() and gops.fb.dump_wpr_info() Also unset HALs accessing VPR registers on dGPUs We don't support VPR on dGPUs Remove fb_mmu_vpr_info_r() register and all its accessors from dGPU headers Bug 2173122 Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850947 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove big page setting on pascal+Deepak Nibade2018-09-29
| | | | | | | | | | | | | | | | | | | | | We don't support big page size beginning Pascal, so set HAL gops.fb.set_mmu_page_size() to NULL on all those platforms Also remove these accessors from corresponding platforms fb_mmu_ctrl_use_pdb_big_page_size_v() fb_mmu_ctrl_use_pdb_big_page_size_true_f() fb_mmu_ctrl_use_pdb_big_page_size_false_f() Bug 2173122 Change-Id: I7353412860a7a6f8a993ca9184a0dc3ca9d749af Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1850946 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add gv11b_gr_clear_sm_error_stateAnup Mahindre2018-09-27
| | | | | | | | | | | | | | | | | All chips were currently using gm20b_gr_clear_sm_error_state It was wrong for chips based on volta and later as the implementation didn't consider non pes-aware vsms mapping Add new HAL implementation for clear_sm_error_state for volta based and later chips to fix this. Bug 200448172 Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837188 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB reset to MC unitTerje Bergstrom2018-09-27
| | | | | | | | | | | | FB reset is done by accessing MC register. Move the code to MC unit. JIRA NVGPU-954 Change-Id: I1636887af805f016da5490af65e808f9ac015cde Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823385 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add MC APIs for reset masksTerje Bergstrom2018-09-27
| | | | | | | | | | | | | | Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: commonize errs in *get_litter_value()Philip Elcan2018-09-26
| | | | | | | | | | | | | | | | | | | | | | | No one is checking return values for the *get_litter_value() functions in the 100s of references, and some of the *get_litter_value() functions were already doing a BUG(), we'll just call BUG() in all them. And since we don't return in the error case, and there's no guarantee that an errno won't collide with the litter values, we'll just initialize the local ret value to 0 to avoid problems and confusion. JIRA NVGPU-647 Change-Id: Id974c904a142c4b3abf1ab940121c270208b0b83 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830582 GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix return type of *get_litter_value()Philip Elcan2018-09-26
| | | | | | | | | | | | | | | | | | | | | | All callers for the *get_litter_value() functions were expecting u32, but the functions were declared to return int's. This is a violation of MISRA 10.3 which prohibits implicit assignment between essential types (signed int and unsigned long int, in this case). The litter values are all u32's anyway. JIRA NVGPU-647 Change-Id: I853d2abee372488e5d12e355050cbeaf1e53a42c Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1830581 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable HWPM Mode-E context switchVaibhav Kachore2018-09-26
| | | | | | | | | | | | | | | | | | | | | | | | | | | - This patch enables HWPM Mode-E context switch for gv11b. - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: Idc6380116a71ffd7ae348ceec68cb395b2eca5f6 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818070 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU init sequence changeMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR code refactorMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: PMU cleanup for ACRMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | - Removed ACR support code from PMU module - Deleted ACR related ops from pmu ops - Deleted assigning of ACR related ops using pmu ops during HAL init -Removed code related to ACR bootstrap & dependent code for all chips. JIRA NVGPU-1147 Change-Id: I47a851a6b67a9aacde863685537c34566f97dc8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817990 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"Konsta Holtta2018-09-21
| | | | | | | | | | | | | This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb. Bug 2400508 Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837223
* gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctlaalex2018-09-21
| | | | | | | | | | | | | | | added hal layer for SM exception mask handling for taking care of vitualization case. Jira VQRM-4806 Bug 200447406 Bug 2331747 Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544 Signed-off-by: aalex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816284 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add igpu support for clk_arbiter.Debarshi Dutta2018-09-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch constructs clk_arbiter specific code for gp10b as well as gv11b and does the necessary plumbing in the clk_arbiter code. The changes made are as follows. 1) Constructed clk_arb_gp10b.* files which add support for clk_arb related HALS including the nvgpu_clk_arb_init and nvgpu_clk_arb_cb. This doesn't have support for debugfs nor the VFUpdateEvent yet and consequently no support for arb->notifications. 2) Added gpcclk specific variables corresponding to every gpc2clk in a given clk_arb related struct. 3) Linux specific support_clk_freq_controller is assigned true in platform_gp10b.c and platform_gv11b.c files. 4) Incremented the clk_arb_worker.put atomic variable during worker_deinit so as to allow the worker thread to be stopped. 5) Added the flag clk_arb_events_supported as part of struct nvgpu_clk_arb. This flag is used to selectively account for the extra refcounting present in OS specific code i.e. nvgpu_clk_arb_commit_request_fd. For igpus, the extra refcount is reduced during nvgpu_clk_arb_release_completion_dev. Bug 2061372 Change-Id: Id00acb106db2b46e55aa0324034a16a73723c078 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774281 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE APIAnup Mahindre2018-09-19
| | | | | | | | | | | | Remove the API as it has no use cases. Bug 200445906 Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move MC HAL to commonTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | | | | | | Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove unused regops HALsDeepak Nibade2018-09-05
| | | | | | | | | | | | | | | | | | | | Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel header to commonKonsta Holtta2018-09-05
| | | | | | | | | | | | | channel_gk20a is clear from chip specifics and from most dependencies, so move it under the common directory. Jira NVGPU-967 Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810578 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Bump FB gk20a code to gm20bTerje Bergstrom2018-09-04
| | | | | | | | | | Move all code from fb_gk20a.c to fb_gm20b.c. Change-Id: I87fbdfee76599e019564d66bf248aaffcf978498 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801422 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split HUB and GPC MMU debug mode setTerje Bergstrom2018-09-04
| | | | | | | | | | | | HUB and GPC MMU debug modes were set in the same function. This introduced a dependency from FB code to GR registers. Split setting of GPC MMU debug mode to GR HAL. Change-Id: I003446f9dfa147f526bd01d3b6130f4037d9b183 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1801420 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use debug sig for NVDEC if on dbg SKUTerje Bergstrom2018-08-31
| | | | | | | | | | | | | | Debug fused chips do not have production signature. Use debug signature for memory unlock binary. Requires also exporting a HAL for checking debug mode from PMU. Bug 200445202 Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809225 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "Revert "gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer""Seshendra Gadagottu2018-08-29
| | | | | | | | | | | | | This reverts commit d029ad5d8d39e7f153b43ca9d60c0ed1f23c8037. Bug 200441252 Change-Id: I1fe7cd1c9446d6572711b050e946b03605acf422 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HALDebarshi Dutta2018-08-29
| | | | | | | | | | | | | | | | | | | | In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Fix MISRA 15.6 violationsSrirangan2018-08-28
| | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I1562bd1b109a100af29bd147ed8b56463b6a8e63 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796674 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Scott Long <scottl@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse HAL to commonTerje Bergstrom2018-08-20
| | | | | | | | | | | | Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
* gpu: nvgpu: Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHEAnup Mahindre2018-08-17
| | | | | | | | | | | | | | | | | Deprecate NVGPU_GPU_IOCTL_INVAL_ICACHE as it is unused and has a broken implementation. Bug 200439908 Change-Id: Iab6f08cf3dd4853ba6c95cbc8443331bf505e514 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1800797 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ltc HAL to commonTerje Bergstrom2018-08-16
| | | | | | | | | | | | Move implementation of ltc HAL to common/ltc. JIRA NVGPU-956 Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1798461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move therm HAL to commonTerje Bergstrom2018-08-14
| | | | | | | | | | | | | | | Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move priv_ring HAL to commonTerje Bergstrom2018-08-13
| | | | | | | | | | | | | | | | | Move implementation of priv_ring HAL to common/priv_ring. Implement two new HAL APIs to remove illegal dependencies: enable_priv_ring and enum_ltc. As enum_ltc can be implemented only gm20b onwards, bump gk20a implementation to base on gm20b. JIRA NVGPU-964 Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797025 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move exec_reg_ops() to regops HALDeepak Nibade2018-08-10
| | | | | | | | | | | | | | | | | We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations But we have separate gops.regops operations for all the regops and this would be logically correct place for exec_reg_ops() Move exec_reg_ops() from gops.dbg_session_ops to gops.regops Also rename it to exec_regops() Jira NVGPU-620 Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794999 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependencyDebarshi Dutta2018-08-08
| | | | | | | | | | | | | | | | | clk_arb.h and gk20a.h has circular dependencies to each other. This is removed by forward declaring struct gk20a in clk_arb.h and removing the header gk20a.h from clk_arb.h and similarly forward declaring struct nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h alongwith putting headers in every execution unit which calls clk_arb.h related methods. JIRA NVGPU-597 Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: fix PMA list alignment in ctxsw buffer"Vinod Gopalakrishnakurup2018-08-02
| | | | | | | | | | This reverts commit 96d4842c0dbae051258408480b981ed034163c13. Change-Id: Ibcdf78b242c7bb9f17651b2bb9e23777c97cd436 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1790634 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-06-02 12:49:28 -0400