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path: root/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
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* gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLsDeepak Nibade2017-11-15
| | | | | | | | | | | | | | | | | | TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove PTE kind code for GV100/GV11BSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return GPU classes in get_litter_valueTerje Bergstrom2017-11-09
| | | | | | | | | | | | | Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: I92cbadf3bd07292a8715d30843972def879795f5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593691 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv1xx: Move fuse override DT handlingTerje Bergstrom2017-11-09
| | | | | | | | | | | | | | | | | Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split ctxsw_trace API into non-Linux componentAlex Waterman2017-11-01
| | | | | | | | | | | | | | T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linuxAlex Waterman2017-10-29
| | | | | | | | | | | | Fixups for the change of name subject in nvgpu. JIRA NVGPU-287 Change-Id: I6c19733079061a42786b94fc48db374d715ccbef Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1586548 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv1xx: resize patch bufferDavid Nieto2017-10-26
| | | | | | | | | | | | | Follow the sizing consideration in bug 1753763 to support dynamic TPC modes and subcontexts. bug 200350539 Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1584034 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: init_cyclestats fixesPeter Daifuku2017-10-25
| | | | | | | | | | | | | | | | | | - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: use scg perf for smid numberingseshendra Gadagottu2017-10-25
| | | | | | | | | | | | | | | | | | | | | | For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Cleanup generic MM codeAlex Waterman2017-10-24
| | | | | | | | | | | | | | t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv100: fix timeout handlingDavid Nieto2017-10-23
| | | | | | | | | | | | | GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100 memory unlock supportMahantesh Kumbar2017-10-21
| | | | | | | | | | | | | | | | | | - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update css opsseshendra Gadagottu2017-10-20
| | | | | | | | | | | | | | | | | | | | | | Updated following hal functions for css gv11b and reused them for gv100: enable_snapshot disable_snapshot check_data_available These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target based on memory aperture used for hwpm inst_block. Bug 200327596 Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1507546 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv1xx: Remove HAL for restore_context_headerseshendra Gadagottu2017-10-20
| | | | | | | | | | | | gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Refactoring nvgpu_vm functionsAlex Waterman2017-10-18
| | | | | | | | | | | | | | | | | Change required for equivalent change on nvgpu. This is required since a few HALs were added that must be populated for all chips. This patch adds those HAL definitions for gv11b, gv100, and the vgpu. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I65374764350a5cacce8624b15d98947fada35a4a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579865 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update dbg opsseshendra Gadagottu2017-10-18
| | | | | | | | | | | | | | | | | | | | | Updated following hal functions for gv11b and reused them for gv100: perfbuffer_enable perfbuffer_disable These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target to sys_ncoh_f(). Bug 200327596 Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1571074 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: vgpu: flatten out t19x vgpu halPeter Daifuku2017-10-13
| | | | | | | | | | | | | | | | | Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574619 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: perfbuffer enable and disable dbg ops set to NULLSeema Khowala2017-10-10
| | | | | | | | | | | | | | Will be enabled after feature is verified on volta Bug 200352825 Change-Id: Idbe318ea82051e53f15caecf2afb15d72b99acea Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574482 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: verify channel status while closing per-platformDeepak Nibade2017-10-04
| | | | | | | | | | | | | | | | We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify channel status while unbinding a channel from TSG while closing Add support to do this verification per-platform and keep this disabled for vgpu platforms Bug 200327095 Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1572369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename ops.mm.get_physical_addr_bitsAlex Waterman2017-10-04
| | | | | | | | | | T19x/gv100 version of same patch in kernel/nvgpu. Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566750 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: init therm regs for pwr/clkSeema Khowala2017-10-03
| | | | | | | | | | | | | | | init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: fix handling of EGPC_ETPC_SM addressesseshendra Gadagottu2017-09-26
| | | | | | | | | | | | | | | | | | | | | | Implemented litter values for following defines: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Added broadcast flags for smpc Handled all combinations of broadcast/unicast EGPC, ETPC, SM Bug 200337994 Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1539075 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Change license for common files to MITTerje Bergstrom2017-09-25
| | | | | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add support for WPR info read from FBMahantesh Kumbar2017-09-22
| | | | | | | | | | | | | | | | update .read_wpr_info HAL of gv11b & gv100 to point to gm20b_fb_read_wpr_info() JIRA NVGPU-128 Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1564684 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Initialize ctxsw hdr countersseshendra Gadagottu2017-09-19
| | | | | | | | | | | | | | | | | | | | | | | | | Initlize following context switch header counters for gv11b: ctxsw_prog_main_image_num_save_ops ctxsw_prog_main_image_num_restore_ops ctxsw_prog_main_image_num_wfi_save_ops ctxsw_prog_main_image_num_cta_save_ops ctxsw_prog_main_image_num_gfxp_save_ops ctxsw_prog_main_image_num_cilp_save_ops Reused gp10b gr hal function gr_gp10b_init_ctxsw_hdr_data() for this. Bug 1958308 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Change-Id: I10d83e35ccd8cba517ebaba1f0e5bec5a0f68ba5 Reviewed-on: https://git-master.nvidia.com/r/1562655 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: fecs_trace ops are set to NULLSeema Khowala2017-09-15
| | | | | | | | | | | | | | CTXSW_TRACE will be enabled only after it is verified. Set all function pointers for fecs_trace to NULL JIRA GPUT19X-42 Change-Id: I7a807f997f683c19541e55fa7e3d5d3ff6b645d2 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1558464 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add tsg_verify_status_faulted operationDeepak Nibade2017-09-15
| | | | | | | | | | | | | | | | | | | | | Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add TSG enable/disable operationsDeepak Nibade2017-09-15
| | | | | | | | | | | | | | | | | | | | | | Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add ops for getting timestamp.Deepak Goyal2017-09-11
| | | | | | | | | | | | | | | | assign GPU bus ops for getting timestamps using PTIMER. BUG 1957272 Change-Id: I1ded165858849a6a93e6ae0617ec1423d48f75ed Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1555528 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Secure boot support.Deepak Goyal2017-08-31
| | | | | | | | | | | | | | This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg gr HAL initializationSunny He2017-08-24
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct NUM_FBPASPeter Daifuku2017-08-22
| | | | | | | | | | | | | | | Although igpu does not have an FBPA unit, the hardware reports one, and the ucode leaves space for one in the HWPM context save buffer. So let NUM_FBPAS reflect this, so that registers that follow this section in the context buffer are offset properly JIRA EVLR-1716 Change-Id: I067d5ec3afd356bcb4270fc2b5d12daef2ce3944 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1535274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Reorg pmu HAL initSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reorg mm HAL initializationSunny He2017-08-14
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg fb HAL initializationSunny He2017-08-14
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: PPC_IN_GPC_SHARED_BASE litterSandarbh Jain2017-08-14
| | | | | | | | | | | | | | Adding missing GPU_LIT_PPC_IN_GPC_SHARED_BASE litter value Bug 1971835 Change-Id: If8851971ebea685fd6b3515b740aba8b64cae067 Signed-off-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1536084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: gv11b: Reorg fb HAL initialization"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit da8e67f042760d54f3d6b5f84abbd9981d9fcd54. Change-Id: Ifd1a51debc0e92fc443e6ac0aad1b224821d6585 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537669 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* Revert "gpu: nvgpu: gv11b: Reorg mm HAL init"Sunny He2017-08-11
| | | | | | | | | | | This reverts commit 96615351ad11a186f5869e56acb3c1948ab7b7cc, which conflicts with gv100 changes. Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537667 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* gpu: nvgpu: gv11b: Reorg mm HAL initSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg fb HAL initializationSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I896d90e0dcffc0e133e6902ff9c3eab39c53080d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533354 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update gv11b_get_litter_valuePeter Daifuku2017-08-07
| | | | | | | | | | | | | | | | Update gv11b_get_litter_value: - add PPC_IN_GPC_BASE - set all FBPA values to 0, since gv11b does not have an FBPA unit - error/bug if we fall through to default, for easier debugging JIRA EVLR-1712 Change-Id: I9a388d6f525e101d4742ade07f972410ec3b2591 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533192 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Make LTC disabling common codeTerje Bergstrom2017-08-04
| | | | | | | | | | | | | | | | | | Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: I7b73625bccd45aefa5694989adbf4a0bbac75fc4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1529054 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Reorg regops HAL initializationSunny He2017-08-02
| | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the regops sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ibf9f64ca445691e252b72c2b8fc59edb84e226ce Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530136 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Tested-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg therm HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527423 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg fecs_trace HAL initSunny He2017-07-27
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fecs_trace sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527420 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg gr_ctx HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr_ctx sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Icc6b0f968f2e3209de190d445c878a4b20bfcf4a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527418 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg ce2 HAL initializationSunny He2017-07-27
| | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1509633 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Remove privsecurity from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525714 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Remove securegpccs from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I487aa5e8545027a3b5bbe33ce68b2715cc2eb39a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514096 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: Reorg fifo HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-27 15:40:32 -0400