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* gpu: nvgpu: Add ECC Support for GV11B in LinuxDebarshi Dutta2021-05-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement nvgpu plumbing to allow reporting ECC errors(corrected and uncorrected) to a L1SS service(if one exists). This patch includes the following 1) Added code that submits ECC error reports via the Interrupt context directly to a L1SS service in linux OS. 2) Added support for enabling/disabling the error reports via L1SS's registration/deregistration API. Nvgpu simply invokes an empty function until the registration is successful. 3) Added Spinlock to correctly handle concurrency for accessing the correct Ops for submitting requests. 4) Adds error reporting for a subset of interrupts that can be verified via external ECC injection logic. A subsequent patch will add the API for rest of the interrupts. 5) In case of critical(uncorrected errors), change nvgpu's state to quiesce state. Jira L4T-1187 Bug 200700400 Change-Id: Id31f70531fba355e94e72c4f9762593e7667a11c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2530411 Tested-by: Bibek Basu <bbasu@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: wait ACK for FECS watchdog timeoutDeepak Nibade2020-07-14
| | | | | | | | | | | | | | | | | | | On Volta, nvgpu needs to wait for explicit ACK from CTXSW while setting FECS watchdog timeoout This is manual port of the fixes 4d7e5026e38528b88a4a168eca9a8b180475b368 and ad89436b03428a42e43042b6a849c15843fdebc4 on dev-main since clean cherry-pick is not possible due to huge file and structure differences. Bug 200603566 Change-Id: Icba69998ab45eee5fdf2a29e1ac1067589301be6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2371708 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add speculative barrierRanjanikar Nikhil Prabhakarrao2020-06-30
| | | | | | | | | | | | | | | | | | | | | | Data can be speculativerly stored and code flow can be hijacked. To mitigate this problem insert a speculation barrier. Bug 200447167 Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08 Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1972221 (cherry picked from commit f0762ed4831b3fe6cc953a4a4ec26c2537dcb69f) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/1996052 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Deepak Nibade <dnibade@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable platform atomic featureVinod G2020-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. bug 200580236 Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2013481 (cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1) Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274932 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H <sh@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allocate ctxsw buffers once onlyPeter Daifuku2019-01-31
| | | | | | | | | | | | | | | | | In *_set_ctxsw_preemption_mode, only allocate buffers the first time through. Bug 200418468 Change-Id: I22d06463416615b9a9d671c32b6fe76b602a2623 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2004301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Satish Arora <satisha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL-ify pmm type broadcast valuesmatthewb2018-10-11
| | | | | | | | | | | | | | | | | | | | The PMM type-specific broadcast->unicast expansion calculation was using incorrect values. This caused the invalid register accesses to be generated. This change HAL-ifies the values, so that the expansion will be performed correctly. Bug 200454109 Change-Id: I96c15de27b5e16e4db2e788fd98e6bf7d6e7d564 Signed-off-by: Matthew Braun <matthewb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921717 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add gv11b_gr_clear_sm_error_stateAnup Mahindre2018-09-27
| | | | | | | | | | | | | | | | | All chips were currently using gm20b_gr_clear_sm_error_state It was wrong for chips based on volta and later as the implementation didn't consider non pes-aware vsms mapping Add new HAL implementation for clear_sm_error_state for volta based and later chips to fix this. Bug 200448172 Change-Id: I65988c8cbb35d13089ac628e8333d9a3b58e0eb1 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1837188 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gpu: Support multiple tpc-pg masks.Deepak Goyal2018-09-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - TPC powergating should be done before calling gk20a_enable_gr_hw. gk20a_enable_gr_hw() issues a GR engine reset. Without this fix, enabling 1 TPC from each PES causes ctxsw timeout error while running GFX Benchmark. - Adds valid tpc-pg mask for 1/2/3/4 active TPC configs. TPC Config - TPC-MASK 4 TPC configuration - 0x0 3 TPC configuration - 0x1/0x2/0x4/0x8 2 TPC configuration - 0x5/0x9/0x6/0xa - We should not write to gr_fe_tpc_pesmask_r() as part of TPC-PG sequence. This register is for debug purpose only. Bug 200442360 Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809772 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE APIAnup Mahindre2018-09-19
| | | | | | | | | | | | Remove the API as it has no use cases. Bug 200445906 Change-Id: Ia2803bd05d78853963011a67091b34ba5bdb3732 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1817629 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Wait for empty always has GR enabledTerje Bergstrom2018-09-13
| | | | | | | | | | | | | | | | | | Whenever wait for empty HAL is called, GR is out of reset. Check for GR being out of reset was adding an extra dependency to MC, so just remove that code. JIRA NVGPU-964 Change-Id: Ic6d607fd2e29359a67896973517d8de6542029e9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813522 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix vsm mapping used by gv11b_gr_set_sm_debug_modeAnup Mahindre2018-09-10
| | | | | | | | | | | | | | Mapping used by gv11b_gr_set_sm_debug_mode is inconsistent with mapping exposed via gk20a_ctrl_vsm_mapping as it doesn't consider non pes aware GPC/TPC to SM mapping. Bug 200448172 Change-Id: Id8a7208a779e577377464f632b819bc0cb228e92 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Return gr_ctx_resident from NVGPU_DBG_GPU_IOCTL_REG_OPSAnup Mahindre2018-09-09
| | | | | | | | | | | | | | | | | | NVGPU_DBG_GPU_IOCTL_REG_OPS currently doesn't return if the ctx was resident in engine or not. Regops are broken down into batches of 128 and each batch is executed together. Since there only 32 bits were available in IOCTL args, returning is ctx was resident isn't possible for all batches. Hence return if the ctx was resident for the first batch. Bug 200445575 Change-Id: Iff950be25893de0afadd523d4ea04842a8ddf2af Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1812975 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: move channel header to commonKonsta Holtta2018-09-05
| | | | | | | | | | | | | channel_gk20a is clear from chip specifics and from most dependencies, so move it under the common directory. Jira NVGPU-967 Change-Id: I41f2160b96d4ec84064288ecc22bb360e82352df Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1810578 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert "gpu: nvgpu: gv11b: enable RMW for gpu atomics"Richard Zhao2018-09-04
| | | | | | | | | | | | | | | | The original change caused cuda atomic perf regression. Bug 2310618 This reverts commit 10c3d4447d4206302f5d51695bf1f193255dd889. Change-Id: Iea5391a89fdfadfb9a79cda57e71f1c9e87ca882 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793880 (cherry picked from commit d0e51ddcb8139de70916335f124a80b8b588308b) Reviewed-on: https://git-master.nvidia.com/r/1804945 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move SM_MASK_TYPE setting to TSG levelVinod G2018-08-31
| | | | | | | | | | | | | | | | | | | | Moved the SM_MASK_TYPE variable from GR to TSG struct. SM error registers are context based. In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel code iterate the TSG associated with first channel and set the mask_type to that context. Bug 200412641 Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809322 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove ctx header desc typeKonsta Holtta2018-08-31
| | | | | | | | | | | | | | The graphics subctx header object is nothing but memory. Drop the dependency to gr header file in the channel header file and substitute struct nvgpu_mem for struct ctx_header_desc. Jira NVGPU-967 Change-Id: Ic3976391016c42d2ada4aac3e0851a1222244ce9 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807370 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix zbc MISRA 10.1 violationsScott Long2018-08-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The gr_gk20a_add_zbc() routine returns a signed error (errno) status value. Current callers of this function use a bitwise OR to collect the returned error status values to generate a single value to return. Bitwise OR on signed status values is flagged as a violation of MISRA Rule 10.1 (not to mention that in this case it potentially results in a garbage return value). To eliminate such violations this change modifies the following routines to fail immediately on the first error from a call to gr_gk20a_add_zbc(): * gr_gk20a_load_zbc_default_table() * gr_gv11b_load_stencil_default_tbl() JIRA NVGPU-650 Change-Id: If733c1bb0e05943ff5d0355de729133c89233583 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805501 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 10.1-Using boolean as a bitAmulya2018-08-28
| | | | | | | | | | | | | | | | | | Fix violations where a boolean is used as an operand in bit-shift operations and is interpreted as a numerical value. JIRA NVGPU-649 Change-Id: I4494c3b69d0e53319331b47d0a4de0b3de279f4f Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1799322 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Amulya Murthyreddy <amurthyreddy@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Read sm error ioctl support for tsgVinod G2018-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | Add READ_SM_ERROR IOCTL support to TSG level. Moved the struct to save the sm_error details from gr to tsg as the sm_error support is context based, not global. Also corrected MISRA 21.1 error in header file. nvgpu_dbg_gpu_ioctl_write_single_sm_error_state and nvgpu_dbg_gpu_ioctl_read_single_sm_error_state functions are modified to use the tsg struct nvgpu_tsg_sm_error_state. Bug 200412642 Change-Id: I9e334b059078a4bb0e360b945444cc4bf1cc56ec Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794856 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Fix MISRA 15.6 violationsSrirangan2018-08-23
| | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Iba8bf3a69ebba04e30ad3d0d7d1db3e183ecbb3d Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803559 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: Fix nonpes aware tpc mappingPhilemon Gardet2018-08-22
| | | | | | | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG are indexed on nonpes aware tpc. Bug 2096878 Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea Signed-off-by: Philemon Gardet <pgardet@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1783046 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Sandarbh Jain <sanjain@nvidia.com> Tested-by: Sandarbh Jain <sanjain@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse HAL to commonTerje Bergstrom2018-08-20
| | | | | | | | | | | | Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
* gpu: nvgpu: Move ltc HAL to commonTerje Bergstrom2018-08-16
| | | | | | | | | | | | Move implementation of ltc HAL to common/ltc. JIRA NVGPU-956 Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1798461 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move therm HAL to commonTerje Bergstrom2018-08-14
| | | | | | | | | | | | | | | Move implementation of therm HAL to common/therm. ELCG and BLCG code was embedded in gr HAL, so moved that code to therm. Bump gk20a code to gm20b. JIRA NVGPU-955 Change-Id: I9b03e52f2832d3a1d89071a577e8ce106aaf603b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: MISRA 10.4 enum fixesAmulya2018-08-14
| | | | | | | | | | | | | | | | MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: export APIs to handle sw methodsDeepak Nibade2018-08-13
| | | | | | | | | | | | | | | | | | | | Export below APIs in gv11b/gr_gv11b.h header so that they can be called from other files too gr_gv11b_set_shader_cut_collector() gr_gv11b_set_go_idle_timeout() gr_gv11b_set_coalesce_buffer_size() gr_gv11b_set_tex_in_dbg() gr_gv11b_set_skedcheck() gv11b_gr_set_shader_exceptions() Bug 2260560 Change-Id: Ic85e35bc223c88c2a54fab09851b8a957b4d1153 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1793525 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove utils.h from gk20a.hVinod G2018-08-10
| | | | | | | | | | | | | | | | Removed the utils.h include from gk20a.h utils.h is included in those files which make use of the macros in utils.h JIRA NVGPU-1005 Change-Id: Ifb41da58db6ff8682fa6b5dfdd8eda11a751fcac Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1785952 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix MISRA 15.6 violationsSrirangan2018-08-10
| | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces including single statement loop bodies. This patch fix the MISRA violations due to single statement loop bodies without braces by adding them. JIRA NVGPU-989 Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791194 Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add IOCTL for SM_EXCEPTION_TYPE_MASKVinod G2018-08-08
| | | | | | | | | | | | | | | | | Add new ioctl to set the SM_EXCEPTION_TYPE_MASK is added to dbg session. Currently support SM_EXCEPTION_TYPE_MASK_FATAL type If this type is set then the code will skip RC recovery, instead trigger CILP preemption. bug 200412641 JIRA NVGPU-702 Change-Id: I4b1f18379ee792cd324ccc555939e0f4f5c9e3b4 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729792 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: reduce verbosity of TPC PG mask and status being sameLeon Yu2018-08-06
| | | | | | | | | | | | | | | | | | | | | Once tpc_pg_mask is programmed successfully, TPC PG mask and status will be the same value afterwards and won't change. So we don't have to inform user whenever gr_gv11b_powergate_tpc() is invoked. Bug 200406784 Bug 200436857 Change-Id: I52f7bdbbbc0851b59366b1cd7d25ae7b8b9fa14e Signed-off-by: Leon Yu <leoyu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1791008 (cherry picked from commit c8872d61a2bc40e09e137a4bb81923c4747a2dcc) Reviewed-on: https://git-master.nvidia.com/r/1791656 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Deepak Goyal <dgoyal@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: tpc powergating through sysfsDeepak Goyal2018-07-24
| | | | | | | | | | | | | | | | | | | | | | | - adds static tpc-powergating through sysfs. - active tpc count will remain till the GPU/systems is not booted again. - tpc_pg_mask can be written only after GPU probe finishes and GPU boot is triggered. Note: To be able to use this feature, we need to change boot/init scripts of the OS(used with nvgpu driver) to write to sysfs nodes before posting discover image size query to FECS. Bug 200406784 Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742422 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rework ecc structure and sysfsRichard Zhao2018-07-19
| | | | | | | | | | | | | | | | | | | | | - create common file common/ecc.c which include common functions for add ecc counters and remove counters. - common code will create a list of all counter which make it easier to iterate all counters. - Add chip specific file for adding ecc counters. - add linux specific file os/linux/ecc_sysfs.c to export counters to sysfs. - remove obsolete code - MISRA violation for using snprintf is not solved, tracking with jira NVGPU-859 Jira NVGPUT-115 Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1763536 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gv11b: Rearrange gr functionVinod G2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB MMU query to FB HALTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming FB phys access to FBTerje Bergstrom2018-07-09
| | | | | | | | | | | | | FB physical access register for simulation was programmed in GR implementation. Move it to FB where it belongs. JIRA NVGPU-714 Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772915 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Call handle_replayable_fault via HALTerje Bergstrom2018-07-08
| | | | | | | | | | | | | | gr_gv11b.c had a direct dependency to fb_gv11b.c because it calls FB to process replayable faults while waiting for SM lockdown. Redirect that call via HAL to remove the dependency. JIRA NVGPU-714 Change-Id: Ie6df3658f06b1f867893bc98fe581c95813f0431 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772884 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: enable RMW for gpu atomicsAshish Srivastava2018-06-26
| | | | | | | | | | | | | | | | | | | | | Separate HAL added in gv11b and gv100 for init_gpc_mmu function. In gv11b HAL, RMW is enabled for gpu atomics as default. In gv100 HAL, GPC atomic capability mode will get set based on the FB MMU capability. If GPU is connected through NVLINK then mmu will be set to RMW mode, else it will be in L2 mode. Bug 200390336 Change-Id: I224934f83d1762ec864ef8da7265dd01d86893a0 Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735137 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: recover on first interrupt reported for mmu nackAparna Das2018-06-15
| | | | | | | | | | | | | | | | | | | In case of mmu nack error interrupt is received twice through SM reported mmu nack interrupt and mmu fault in undertermined order. Recover on the first received interrupt to avoid semaphore release and skip doing a second recovery. Also fix NULL pointer dereference in function gv11b_fifo_reset_pbdma_and_eng_faulted when channel reference is invalid in teardown path. Bug 200382235 Change-Id: I361a5725d7b6355ebf02b2870727f647fbd7a37e Signed-off-by: Aparna Das <aparnad@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1739804 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: correct calculation of sm_id for .record_sm_error_stateRichard Zhao2018-06-14
| | | | | | | | | | | | | | | | | | Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: handle replayable mmu fault during waiting for SM lockdownRichard Zhao2018-06-14
| | | | | | | | | | | | | | outstanding replayable mmu fault will prevent SM from lockdown, so handle the replayable mmu fault while polling lockdown status. Jira EVLR-2643 Bug 200405202 Change-Id: I811f16ef4394a6cc42a5f37a17e426dd749c5652 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1741997 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Handle all SM errorsVinod G2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | Add the missing register bits to identify the SM errors. Except for mmu_nack error, all other errors are handled using a single function. That function sets the error notifier with GR_EXCEPTION, clears interrupt and triggers recovery process. bug 200402677 JIRA NVGPU-573 Change-Id: Icfaff1f20f1f35adb4cd35ce288ce694845aed3c Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730963 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b/gv100: add SHADER_CUT_COLLECTOR compute classSeema Khowala2018-05-30
| | | | | | | | | | | | | | | | | | | | Support NVC3C0_SET_SHADER_CUT_COLLECTOR s/w method for compute class. This is needed to enable/disable SHADER_CUT_COLLECTOR_STATE. Bug 2108381 Bug 2099681 Change-Id: I228dcc55b6df605aeeee094f872157023e3c783c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730634 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Wei Sun <wsun@nvidia.com> Tested-by: Wei Sun <wsun@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-05-24
| | | | | | | | | | | | | | | Only for T194 A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I7122b223946a1bfa4b11ed8ee782572215313dc1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1680500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add sw method for SHADER_CUT_COLLECTORseshendra Gadagottu2018-05-04
| | | | | | | | | | | | | | | | | | Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR to enable/disable SHADER_CUT_COLLECTOR_STATE. Added support for this sw method in gv11b and gv100. Bug 2108381 Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703662 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: chip revision check for invalidatesseshendra Gadagottu2018-04-25
| | | | | | | | | | | | | | | | | | Only for gv11b A01 version following invalidates are disabled: -CBM alpha and beta invalidations for L2 -SCC pagepool invalidates -SWDX spill buffer invalidates Bug 2053668 Change-Id: I027f923b63b24bbbc054a7d9a377d757994a07ad Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1700981 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: consider floorswept FBPA for getting unicast listDeepak Nibade2018-04-16
| | | | | | | | | | | | | | | | | | | | | | | | In gr_gv11b/gk20a_create_priv_addr_table() we do not consider floorswept FBPAs and just calculate the unicast list assuming all FBPAs are present This generates incorrect list of unicast addresses Fix this introducing new HAL ops.gr.split_fbpa_broadcast_addr Set gr_gv100_get_active_fpba_mask() for GV100 Set gr_gk20a_split_fbpa_broadcast_addr() for rest of the chips gr_gv100_get_active_fpba_mask() will first get active FPBA mask and generate unicast list only for active FBPAs Bug 200398811 Jira NVGPU-556 Change-Id: Idd11d6e7ad7b6836525fe41509aeccf52038321f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694444 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 17:30:17 -0400