| Commit message (Collapse) | Author | Age |
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Implement gr ops to handle MPC exception triggered per TPC
JIRA GPUT19X-69
Change-Id: Ia92b1d51ad896116b25d71e07ed26f1539475be8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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gr_gk20a_handle_sm_exception is initialized to
handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception
is initialized to gr_gv11b_handle_tpc_sm_ecc_exception
to handle sm ecc errors per tpc.
JIRA GPUT19X-75
JIRA GPUT19X-109
Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514039
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Required for multiple SM support and SM register
address changes
JIRA GPUT19X-75
Change-Id: I552bae890a416dc4a430b907641b5b3d09b638c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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init lock_down_sm and wait_for_sm_lock_down gr ops
Required to support multiple SM and register address
changes
JIRA GPUT19X-75
Change-Id: I992d1c0c5a1f559dc57bcef50025fa42913d6761
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514037
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Support SM register changes
JIRA GPUT19X-75
Change-Id: I5d5e702d681398a8a8181d912e8c691c15e265d9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514036
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Required for multiple SM support and sm register address
changes
JIRA GPUT19X-75
Change-Id: I3fb62a935636f3df050ed125ebe57d8469069591
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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get sm hww_warp_esr reg val
JIRA GPUT19X-75
Change-Id: I4ed04045e947c417291b7b1e2fc81bbe51f0b48c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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JIRA GPUT19X-75
Change-Id: Ie741bf50c771f21de3bf762ca506a36276f38437
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512211
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Ia5c0a3d1dead9c6094ca28716c06929dd3461814
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I0ebbfdad73d6212997a21f9240f5d4bc2f28ab2f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512209
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I46b7d58ed02710339aa27cd9db999aa60fbd4dd9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512208
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Take care of SM register address changes.
JIRA GPUT19X-75
Change-Id: I7fa68dbef014fb07a3656b2816d7d8d538a7cf52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512207
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Support gv11b sm register address changes.
JIRA GPUT19X-75
Change-Id: I22562789ef7c064fa36c2d382224af6dc6a806c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512206
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers
JIRA GPUT19X-75
Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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For updating broadcast register, read the current
value from unicast register.
JIRA GPUT19x-75
Change-Id: Ib4a3791304cabe77cf46543d4bec0312c6fcc0fb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511735
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr*
registers instead of *gpcs_tpcs_sm_hww_warp/global_esr*
GPUT19X-75
Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1474860
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Take care of t19x sm reg address changes and support multiple SM
JIRA GPUT19X-75
Change-Id: I675b76b90d08fe75331f0023f1fe722497d06373
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477673
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Support multiple SM and take care of sm reg addr changes
JIRA GPUT19X-75
Change-Id: Id39e269034762c7a8347edaf1fff0b2efd7f153c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477705
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Support multiple SM and take care of SM hardware reg address changes
JIRA GPUT19X-75
Change-Id: I866011a85da06ca22bc10fda5ab59f84d0782902
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477686
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Take care of t19x reg address changes to support multiple SM
JIRA GPUT19X-75
Change-Id: I92b97e60ac82c50a97fe44a85482437446479800
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1477694
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add gv11b specific trigger_suspend function. SM register
addresses have changed as compared to legacy gpu chips.
JIRA GPUT19X-75
Change-Id: Ic3099e53bcba19128711a88ecc9e9883f5f7a31f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1476532
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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/d/gpu.0/gr_status will dump sm registers too
JIRA GPUT19X-75
Change-Id: If5d19c9ef5c05b6390e8e55c39571869d3d01ae7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1500879
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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corrected whitelist address for gr_pri_gpcs_tpcs_sms_dbgr_control0
JIRA GPUT19X-49
Bug 200311674
Change-Id: I512197c4a6ef97a59bbb303e31ab91f7727bf8d5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1499394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Change function name write_preemption_ptr to set_preemption_buffer_va
to match with what exactly getting done in that function.
Change-Id: I91372642f1dba37e5e7bcda29ac9c4271cec4b53
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1510973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Calculate sm reg offset by using gpc, tpc and sm numbers
-Init get_esr_sm_sel gr ops
JIRA GPUT19X-75
Change-Id: I74cfcae07e385cdad51774b963380c0633adfecf
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1506152
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gv11b has multiple SMs and SM register addresses
have changed as compared to legacy chips.
JIRA GPUT19X-75
Change-Id: I2319f4c78f3efda3430bab1f5ecf1a068e57a1ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1506013
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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reuse gr_gp10b_handle_fecs_error and cilp functions
Bug 200289491
Change-Id: I4040f96875ad91d174ce36aab957fb94d79c3a74
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1505952
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added sw method for NVC397_SET_TEX_IN_DBG with
following data fields:
data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE
data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD
data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST
Bug 1934197
Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1507479
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL disabled
Bug 200315442
Change-Id: I6d5c5f2fe6255d480350e01959c3c340579646e2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1499568
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Preempt type should be set to tsg and id should be set to tsgid
in fifo_preempt_r(). Preempt type channel and id set to channel
id does not initiate preemption.
Bug 200289427
Bug 200292090
Bug 200289491
Change-Id: I2ae96c0b9ca8a88a8405f42775744f0879994887
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1497877
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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GPUT19X-70
Change-Id: Ifc6c52ac15108d1389fcd732218abf46b6167485
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1486177
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Adding support for GPC MMU ECC error handling
JIRA: GPUT19X-112
Change-Id: I62083bf2f144ff628ecd8c0aefc8d227a233ff36
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1490772
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Gv11b ucode is not having support for low
latency context-switching. So disable
cfz_bypass mode for now.
JIRA GPUT19X-116
Change-Id: I814cd254fa3c342c20906805a4b13b52c89d5b1e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1494217
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Include <nvgpu/debug.h> explicitly wherever
the debug operations are used
Jira NVGPU-62
Change-Id: I1845e08774b7c211e7fd954937708905f905e069
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1492818
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Enable FE, MEMFMT, DS and GPC exceptions only.
Make sure corresponding HWW_ESR are enabled too.
JIRA GPUT19X-75
Change-Id: Icf47b7e531dd72b59cbc6ac54b5902187f703d61
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1474859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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(1) Re-arrange the structure for ecc counters reporting so multiple
units can be managed
(2) Add counters and handling for additional GPC counters
JIRA: GPUT19X-84
Change-Id: I74fd474d7daf7590fc7f7ddc9837bb692512d208
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485277
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Adding support for ISR handling of GPCCS exceptions
and GCC ECC support
JIRA: GPUT19X-83
Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480997
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add handling of GCC L1.5 parity exception.
JIRA GPUT19X-86
Change-Id: Ie83fc306d3dff79b0ddaf2616dcf0ff71fccd4ca
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1485834
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache
Volta Resiliency Id - Volta-634
JIRA GPUT19X-113
JIRA GPUT19X-99
Bug 1807553
Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This CL covers the following parity support (uncorrected error),
1) SM's LRF
2) SM's CBU
Volta Resiliency Id - Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-110
Bug 1775457
Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1481791
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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This CL covers the following parity support (corrected + uncorrected),
1) SM's L1 tags
2) SM's S2R's pixel PRF buffer
3) SM's L1 D-cache miss latency FIFOs
Volta Resiliency Id - Volta-720, Volta-721, Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-104
JIRA GPUT19X-100
JIRA GPUT19X-103
Bug 1825948
Bug 1825962
Bug 1775457
Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1478881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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React to possible errors in gr_gv11b_commit_inst() from allocating and
updating subcontext header.
Bug 1927306
Change-Id: I668e13ce13af296e9a7badb3b167fa7a7cd26212
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1483043
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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t19x version of same named patch in nvgpu.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I0b176577c0edcdcc587f22a6908045a960f830e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464111
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Added function pointers to check chip specific valid
gfx class and compute class. Also added function pointer
to update ctx header with preemption buffer pointers.
Also fall back to gp10b functions, where nothing
is changed from gp10b to gv11b.
Bug 200292090
Change-Id: I69900e32bbcce4576c4c0f7a7119c7dd8e984928
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1293503
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Functions that are not declared in header files are made static
Bug 200299572
Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1471538
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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t19x part for this change in nvgpu.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I31116b4241076b39a6638273281630a1527bcd35
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464109
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Defined function to get max number of subcontexs
supported and used it where max subcontext count required.
JIRA GV11B-23
Change-Id: I4f6307162486bab1e91cbf66abfee7763c70fe7b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1318146
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: I8c0d8944f625e3c5b16a9f5a2a59d95a680f4e55
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1459822
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gv11b changes to go along with
gpu: nvgpu: Rename nvgpu DMA APIs
In the main nvgpu repo.
JIRA NVGPU-12
Change-Id: I5e28b13448d171e1511ace0842e53700385f8489
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1455213
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Handle gv11b specific of
gpu: nvgpu: Move DMA API to dma.h
In the main nvgpu repository.
JIRA NVGPU-12
Change-Id: I9645c4eedc5f61585d15caeee54db92bc4cca079
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1455212
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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