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* gpu: nvgpu: gv11b: null check for fault_chSeema Khowala2017-03-23
| | | | | | | | | | | | | | | gk20a_gr_get_channel_from_ctx() could return NULL as a result fault_ch could be null JIRA GPUT19X-7 Change-Id: If89507d3d3fa5a95ba75c4a90eb212d0c8b2214a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1323255 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add tpc floor sweeping codeseshendra Gadagottu2017-03-14
| | | | | | | | | | | | | | Added TPC floor sweeping code for gv11b. JIRA GV11B-73 Change-Id: Ib0d05e2d606fe13dff119948fbc9022e8af0fa7f Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1315257 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: gv11b: add gr ops for load tpc maskSeema Khowala2017-03-02
| | | | | | | | | | | | | gr_fe_tpc_fs_r addr is different for t19x Change-Id: Ibae4b7224ffbd4d8366890cd05649b1b66e22f02 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310327 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: reading max veid numberseshendra Gadagottu2017-02-27
| | | | | | | | | | | | | | | | To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Organize semaphore_gk20a.[ch]Alex Waterman2017-02-13
| | | | | | | | | | | | | t19x version. Bug 1799159 Change-Id: I5e4c2a5341909d2e366ebc15adb4cdce70d695c7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1303264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: chip specific init_elcg_modeseshendra Gadagottu2017-02-07
| | | | | | | | | | | | | | | | | Added thermal registers for gv11b. Implemented chip specific init_elcg_mode. In thermal control register, engine power auto control config is removed and added new field for engine holdoff enable signal. JIRA GV11B-58 Change-Id: I412d9a232800d25efbdb0a40f14949d3f085fb0e Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1300119 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update zcull and pm pointersseshendra Gadagottu2017-01-27
| | | | | | | | | | | | | | | | | | Update zcull and perfmon buffer pointers in context header. For gv11b maximum 49 bits gpu va possible. But, zcull and perfmon buffer pointers uses maximum 41 bit va address (258 bytes aligned). To accommodate this, high pointer registers needs to be updated in context header. JIRA GV11B-48 Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1291852 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: restore golden contextseshendra Gadagottu2017-01-20
| | | | | | | | | | | | | | | | Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Ied87164ea1de793d97a4cc6a754150164af04698 Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287500 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: sw methods for shader exceptionseshendra Gadagottu2017-01-18
| | | | | | | | | | | | | Added proper sw methods handling of shader execptions for gv11b. Bug 1834201 Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1283729 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gv11b's wait_idle()Alex Waterman2017-01-18
| | | | | | | | | | | | | | | | The interface for wait_idle() was changed for gk20a, etc, so this change is necessary to update the wait_idle function for gv11b. Similarly for wait_fe() - this needs to no longer use an end_jiffie argument. Bug 1799159 Change-Id: I192159feffda5476269194e7d6ef15b5fe3055bd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280459 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Support Stencil ZBCSeema Khowala2017-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: legacy support with subcontextseshendra Gadagottu2016-12-20
| | | | | | | | | | | | | | | | | gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix sparse warningseshendra Gadagottu2016-11-30
| | | | | | | | | | | | | | | | | Fix following sparse warning by making function as static: $TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5: warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared. Should it be static? Bug 200088648 Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1261891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: support for new littler valuesseshendra Gadagottu2016-11-17
| | | | | | | | | | | | | | | | | Add support for new litter values: GPU_LIT_NUM_SUBCTX GPU_LIT_NUM_SM_PER_TPC Also updated get_litter_value api to use int instead of enum type. JIRA GV11B-21 Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1254857 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: use fuse control read/write APIs for K4.4Shardar Shariff Md2016-11-11
| | | | | | | | | | | | | | Use fuse control read/write APIs when accessing fuse control registers for Kernel version 4.4 Bug 200243956 Change-Id: I3d78ec2733b5f56615fa0b588664570c85557e63 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245826 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: smid programmingseshendra Gadagottu2016-11-03
| | | | | | | | | | | | | | gv11b specific smid table init, smid numbering and smid programing. JIRA GV11B-21 Change-Id: I3a0f8355f2cd90ab1518cd8a5642a0e84202bdf8 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1227096 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: commit global timesliceseshendra Gadagottu2016-11-01
| | | | | | | | | | | | | | | Implement chip specific commit_global_timeslice function. JIRA GV11B-21 Change-Id: I4f852913cb181f62063084c4e118d97148f99056 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243947 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update gr cb callbacksseshendra Gadagottu2016-10-19
| | | | | | | | | | | | | Update gr cb callbacks with gv11b default sizes. Also updated sw method ids for volta. JIRA GV11B-11 Change-Id: I77cccedb7a017f378e2194cef98ea4b0bf7acd6b Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237786 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: update sm arch infoseshendra Gadagottu2016-10-18
| | | | | | | | | | | | | | Use updated register offset for gr_gpc0_tpc0_sm_arch_r() to read and update correct sm arch info. JIRA GV11B-21 Change-Id: I34af2d4a7665d7848bd74bc56a92ff2c861ceac9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237916 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: enable gpc exceptionsSeema Khowala2016-10-17
| | | | | | | | | | | | | | Add function ptr and function for enabling gpc exceptions. Disable Tex exceptions. JIRA GV11B-28 JIRA GV11B-27 Change-Id: Ife8fe22c24da00ae14f68fd977d84d208831eb45 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1236899 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: remove tex exceptionSeema Khowala2016-10-17
| | | | | | | | | | | | update for CL#37320141 JIRA GV11B-27 Change-Id: I095af59ac419b44b3a1e3abc489857d6f533874a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1236274 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: zcull programmingSeema Khowala2016-10-14
| | | | | | | | | | | | | Bug 1735760 Change-Id: Id801efb613b5740389bde5dc2cfff47232d0a0f3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1221582 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: program sw veid bundlesseshendra Gadagottu2016-10-14
| | | | | | | | | | | | | Program hw state with relevant sw veid bundles. JIRA GV11B-11 Change-Id: I2c5e02016ed41db9c9b7f85cc0b401abaa003d37 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1231598 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: setup rop mappingsseshendra Gadagottu2016-10-12
| | | | | | | | | | | JIRA GV11B-21 Change-Id: I7695936bdac4502ceb0bdad4fc029e249eb2f05d Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1224783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: header updates for CL#37119043Seema Khowala2016-09-28
| | | | | | | | | | Bug 1735760 Change-Id: I5216863a25338f14498ae0be58b86993104d4e99 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1222031 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: hw header updateseshendra Gadagottu2016-09-12
| | | | | | | | | | | | | | Updated hw headers to CL#37001916. Some of important changes include new door bell user mode mechanism and new runlist structure. Bug 1735765 Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1205888 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: send only one event to the debuggerCory Perry2016-09-01
| | | | | | | | | | | | | | | | | | | | | | Event notifications on TSGs should only be sent to the channel that caused the event to happen in the first place, not evey channel in the tsg. Any more and the debugger will not be able to tell what channel actually got the event. Worse yet, if all the channels in a tsg are bound to the same debug session (as is the case with cuda-gdb), then multiple nvgpu events for the same gpu event will be triggered, causing events to be buffered and the client to get out of sync. One gpu exception, one nvgpu event per tsg. Bug 1793988 Change-Id: Ifb33b65f09f67b0e323917c7e7ea016fc3676f18 Signed-off-by: Cory Perry <cperry@nvidia.com> Reviewed-on: http://git-master/r/1194207 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post bpt events after processingDeepak Nibade2016-08-10
| | | | | | | | | | | | | | Receive hww_global_esr in gr_gv11b_handle_sm_exception() and pass it to gr_gk20a_handle_sm_exception() Bug 200209410 Change-Id: I57a701a1f1fa560367f78db212c06d4ce361c7f0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1194987 GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use vidmem by default in gmmu_alloc variantsKonsta Holtta2016-07-08
| | | | | | | | | | | | | | | | | | For devices that have vidmem available, use the vidmem allocator in gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem. Because all of the buffers haven't been tested to work in vidmem yet, rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at the end to declare explicitly that vidmem is used. Enabling vidmem for each now is a matter of removing "_sys" from the function call. Jira DNVGPU-18 Change-Id: Ieb13c21c774380ac0be9987e177b4adc0a647abb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1176810 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: update code to HW CL 36758735seshendra Gadagottu2016-07-07
| | | | | | | | | | | | | Update headers and corresponding code to work with HW CL # 36758735 Bug 1735760 Change-Id: Ie26bfaa6377ab797c5ad978e4796a55334761b5d Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1175882 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11x: support in-kernel vidmem mappingsKonsta Holtta2016-07-06
| | | | | | | | | | | | | | | Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that buffers represented as a mem_desc and present in vidmem can be mapped to gpu. JIRA DNVGPU-18 JIRA DNVGPU-76 Change-Id: I67d476b2c1b84218217ef203e429fb5e8a33adc7 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169297 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove hard coded runlist_id mappingLakshmanan M2016-06-13
| | | | | | | | | | | | | | | From this patch onwards, runlist_id is a member of struct channel_gk20a. So removed hard coded runlist_id mapping logic. JIRA DNVGPU-25 Change-Id: Ia02feffdc057b0dceab9721423feeed1cc7a1c12 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161779 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix patch write error check in update_ctxsw_preemption_modeKonsta Holtta2016-06-06
| | | | | | | | | | | | Don't attempt to access memory if the patch context can't be mapped, but print an error message instead. Change-Id: I2d0ec22378ace0ef826f5a84a9ce4d35466f7832 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157281 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Use gp10b GR floorsweepingTerje Bergstrom2016-05-16
| | | | | | | | Use gp10b version of GR floorsweeping function. Change-Id: I5715672b5f94b779165f44c78aec14a2836928e7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1144905
* gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmemKonsta Holtta2016-05-13
| | | | | | | | | | | | | | | | | To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. JIRA DNVGPU-23 Change-Id: Ie2cc17c4a0315d03a66e92fb635c217840d5399e Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1128863 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: use preemption modes defined in nvgpu-t18x.hDeepak Nibade2016-05-09
| | | | | | | | | | | | | | | | | | | | Below definitions of preemption modes are deleted: NVGPU_GR_PREEMPTION_MODE_GFXP NVGPU_GR_PREEMPTION_MODE_CILP Use new definitions defined in nvgpu-t18x.h NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP NVGPU_COMPUTE_PREEMPTION_MODE_CILP Bug 1646259 Change-Id: Ieff51e41ef34eb61357f95778c400c8a3fa330c8 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1133597 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
| | | | | | | | | | | | | | Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: added initial source codeSeshendra Gadagottu2016-04-13
Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-17 18:09:33 -0400