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path: root/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
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* gpu: nvgpu: gv100: fix timeout handlingDavid Nieto2017-10-23
| | | | | | | | | | | | | GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Change license for common files to MITTerje Bergstrom2017-09-25
| | | | | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add tsg_verify_status_faulted operationDeepak Nibade2017-09-15
| | | | | | | | | | | | | | | | | | | | | Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add TSG enable/disable operationsDeepak Nibade2017-09-15
| | | | | | | | | | | | | | | | | | | | | | Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Reorg fifo HAL initializationSunny He2017-07-24
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: add mmu fault handlingSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: support for full subcontextseshendra Gadagottu2017-07-05
| | | | | | | | | | | | | | | | | Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: add a function to reset pbdma and eng faultedSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: implement eng method buffer init/deinitSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | | | When CE hits a page fault it needs to save out methods, it will save it out to a per runqueue per TSG method buffer. The method buffers (one per TSG runqueue) are allocated in BAR2 space during TSG creation All channels in a TSG that are mapped to the same runqueue will point to the same buffer. S/w will insert channel's method buffer pointer in the channel's instance block entries NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO and NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI. Method buffer in memory will be 32B aligned. Eng method buffer allocated per tsg will be de-allocated during tsg_release. JIRA GPUT19X-46 Change-Id: Ib480ae5840d9815d24fe2eadc169ac3102854cd0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1509747 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout opsSeema Khowala2017-04-12
| | | | | | | | | | | | | | | | | | | - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo opsSeema Khowala2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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