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path: root/drivers/gpu/nvgpu/gv11b/fb_gv11b.h
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* gpu: nvgpu: gv11b: MMU parity HWW error intrDavid Nieto2017-05-11
| | | | | | | | | | | | | | | | | Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>