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path: root/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
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* gpu: nvgpu: gv11b: fbhub: num_ltcs are read onlyseshendra Gadagottu2017-06-21
| | | | | | | | | | | | | | | | In gv11b fbhub num_ltcs is read only, even though register spec says it is rw. The number of ltcs are populated by hw and no need for sw to set those values. GPUT19X-70 Change-Id: Ib9861894cacb70cf54b4958083e55d39a3a85e19 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1497992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: ltc reset seqeunce changeseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | Access ltc registers only after bringing ltc out reset. Earlier ltc bought out of reset in fb_reset which is later than accessing ltc registers. GPUT19X-70 Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1495167 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: move cbc init to mmu from ltcseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | | | | Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: add chip specific ECC countersDavid Nieto2017-06-04
| | | | | | | | | | | | | Add support for ECC counters for HUB MMU JIRA: GPUT19X-82 Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490825 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set only valid soc creditsseshendra Gadagottu2017-06-01
| | | | | | | | | | | | | | | | | | | | | | | Only for following instances, mssnvlink <-> hshub will be interacting in gv11b: NV_ADDRESS_MAP_MSS_NVLINK_1_BASE NV_ADDRESS_MAP_MSS_NVLINK_2_BASE  NV_ADDRESS_MAP_MSS_NVLINK_3_BASE NV_ADDRESS_MAP_MSS_NVLINK_4_BASE   NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub, so don't set those credits. GPUT19X-116 Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1493641 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Update nvlink soc ceditsseshendra Gadagottu2017-05-29
| | | | | | | | | | | | This temp fix will be modified to call proper nvlink module API, once it is available. Change-Id: Id6e9651452a7d7072c285ab00330c85928cdf4d6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1489068 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: MMU parity HWW error intrDavid Nieto2017-05-11
| | | | | | | | | | | | | | | | | Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set soc credits after fs_hub is out of resetSeema Khowala2017-04-18
| | | | | | | | | | | | Without these credits, gpu mmu binds over nvlink to soc are hanging. Also add l2_enabled for mc_elpg_enable. Bug 1899460 Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1463204 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: ngpu: gv11b: support hub interruptSeema Khowala2017-03-30
| | | | | | | | | | | | | | Hub interrupt handler will be added later JIRA GPUT19X-7 Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: bl compressionSeema Khowala2016-10-25
| | | | | | | | | | | | | updated mmu pte kind JIRA GV11B-8 Change-Id: I2baff42e077411a9c72b0d10739f4a45d4bd79a7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1234567 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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