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* gpu: nvgpu: gv11b: dump more mmu fault infoSeema Khowala2018-01-26
| | | | | | | | | | | | | | | | | | | | | -Dump client type/id and protected mode as error prints. This will help figuring out which client is causing mmu fault. -Removed extra print for unbound instance block fault as it is already printed as fault type -Changed few extra prints from info prints to prints protected by gpu_dbg_intr Change-Id: I9e87e2a701372b47200f85149e040176365bd71c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1643817 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fold T19x code back to main code pathsTerje Bergstrom2018-01-23
| | | | | | | | | | | | | Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Suppress nvlink credits init msgTerje Bergstrom2018-01-09
| | | | | | | | | | | | | | Suppress message indicating nvlink credits initialization. Change-Id: I8cd9c64c10412cea783b3d3eeb271a3e1c68d29f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1632780 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: mc_elpg_enable & soc credit init moved to bpmpSeema Khowala2017-11-14
| | | | | | | | | | | | | | | | | | | | | | | | | -Program mc_elpg_enable and mss nvlink soc credits only when bpmp is not running or bpmp is running but underlying platorm is simulation. For simulation, bpmp does not execute hot reset sequence. As part of gpu unpowergate, bpmp will program mc_elpg_enable and also set mss nvlink soc credits after bringing mss nvlink out of reset -Remove updating mc_enable as writes to this register has no effect -Remove fifo_fb_iface_r read/write. This hack was added during initial bring up of emulation platforms Bug 2018223 Bug 200269361 Change-Id: Ie09c259e48295a93c6d15376308186152db973fa Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1594495 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove PTE kind code for GV100/GV11BSami Kiminki2017-11-10
| | | | | | | | | | | | | | | | Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: replay invalid pte faults onlySeema Khowala2017-11-01
| | | | | | | | | | | | | | | | | | Try to fix invalid pte type repalayable faults only. All other replayable faults will be cancelled so that next mmu fault for same fault address will be triggered as non-replayable fault and ch/tsg teardown will take place. Bug 1958308 Change-Id: I63b90ce7c639ee183f87db3e771f253fd04c3567 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1566576 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix faulted channel's id/typeSeema Khowala2017-11-01
| | | | | | | | | | | | | | | | | | | Teardown function should be passed appropriate id and id_type. E.g. if a channel is marked as tsg, channel teardown/rc function should be passed it's tsgid as id and type_tsg as id_type Bug 200277163 Change-Id: I2e83561c03d515fac28cbb8ce75a9f2c7bf746ac Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1557296 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove phys_addr_t from common codeAlex Waterman2017-10-11
| | | | | | | | | | | | | | | | | Remove phys_addr_t change for corresponding change in the nvgpu main repo. JIRA NVGPU-30 JIRA NVGPU-226 Change-Id: I05a19bc51e949279edef6e9ad7161226cbca51a7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1576466 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Change license for common files to MITTerje Bergstrom2017-09-25
| | | | | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Nvgpu abstraction for linux barriers.Debarshi Dutta2017-08-22
| | | | | | | | | | | | | | | | | | construct wrapper nvgpu_* methods to replace mb,rmb,wmb,smp_mb,smp_rmb,smp_wmb,read_barrier_depends and smp_read_barrier_depends. NVGPU-122 Change-Id: I97380c3b211733e682f198c35f35640af203359c Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1541197 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Reorg fb HAL initializationSunny He2017-08-14
| | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove kind map inheritanceSunny He2017-08-14
| | | | | | | | | | | | | | | | | | | | Currently, the kind map initialization inherits from earlier chips' kind map definitions and simply adds on newly supported features. This is dangerous as changes in older architectures may affect newer architectures in unpredictable ways. This patch removes inheritance between subsequent architectures' kind map initializations. Jira NVGPU-74 Change-Id: Iab504d45b6ce2e625ed6788e62c1e7104e45c89a Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537747 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: gv11b: remove kind map inheritance"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit 2660d1d881d1536c1b723d9737ae9a04321d69f3. Change-Id: Id64e1353069aab2155fb0688b55cc7ce3b092516 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537672 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* Revert "gpu: nvgpu: gv11b: Reorg fb HAL initialization"Sunny He2017-08-11
| | | | | | | | | | | | Conflicts with gv100 changes This reverts commit da8e67f042760d54f3d6b5f84abbd9981d9fcd54. Change-Id: Ifd1a51debc0e92fc443e6ac0aad1b224821d6585 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537669 Reviewed-by: Shu Zhong <shuz@nvidia.com> Tested-by: Shu Zhong <shuz@nvidia.com>
* gpu: nvgpu: gv11b: Reorg fb HAL initializationSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I896d90e0dcffc0e133e6902ff9c3eab39c53080d Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533354 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: remove kind map inheritanceSunny He2017-08-11
| | | | | | | | | | | | | | | | | | | | Currently, the kind map initialization inherits from earlier chips' kind map definitions and simply adds on newly supported features. This is dangerous as changes in older architectures may affect newer architectures in unpredictable ways. This patch removes inheritance between subsequent architectures' kind map initializations. Jira NVGPU-74 Change-Id: I894e08da9acd288a4ea36282a2c7dc0b03bf9161 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1533353 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove mm.get_iova_addrAlex Waterman2017-08-04
| | | | | | | | | | | | Volta changes for equivalent change on nvgpu. JIRA NVGPU-30 Change-Id: I78e84ce67468dfe3556232ddb25e824f6b84835c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530863 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: fix get ptr update for mmu fault bufferAshish Srivastava2017-08-02
| | | | | | | | | | | | | | | | | Skipping the last entry makes get ptr 0. This causes HW to think that buffer overflow has happened, but it really hasn't. Due to this issue no further progress is possible as all FB entries beyond get ptr are invalid. Bug 200300788 Change-Id: I7373dfa087cdb7c307aacacf62ef4ca8a0214cf2 Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1528070 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: fix for replay fault addr equal to 0Seema Khowala2017-07-19
| | | | | | | | | | | | | | | fault_addr "0" is not supposed to be fixed ever. For the first time when prev = 0, next = 0 and fault addr is also 0 then handle_mmu_fault_common will not be called. Fix by checking fault_addr not equal to 0 Bug 200277163 Change-Id: I532bca54a85e540415b9f5f5e71daec9cf0e0619 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1522653 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: recover from replay and ce mmu faultSeema Khowala2017-07-12
| | | | | | | | | | | | Fix pte valid bit for replayable fault and ce fault JIRA GPUT19X-12 Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1515538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gv11b: fifo recovery for nonreplay faultSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | Host will no longer receive replayable or non-replayable fault requests. MMU will handle both types of fault reporting. This means that Host will no longer automatically disable scheduling or preempt a PBDMA when an engine page faults. After fault happens, engine will stall on its own fault and will not context switch until the fault is serviced JIRA GPUT19X-7 Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493417 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: add mmu fault handlingSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: set up for enabling/handling hub intrSeema Khowala2017-07-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -implement mm ops init_mm_setup_hw This will also call *fault*setup* that will do s/w and h/w set up required to get mmu fault info -implement s/w set up for copying mmu faults Two shadow fault buffers are pre allocated which will be used to copy fault info. One for copying from fault snap registers/nonreplayable h/w fault buffers and one for replay h/w fault buffers -implement s/w set up for buffering mmu faults Replayable/Non-replayable fault buffers are mapped in BAR2 virtual/physical address space. These buffers are circular buffers in terms of address calculation. Currently there are num host channels buffers -configure h/w for buffering mmu faults if s/w set up is successful, configure h/w registers to enable buffered mode of mmu faults -if both s/w and h/w set up are successful, enable corresponding hub interrupts -implement new ops, fault_info_buf_deinit This will be called during gk20a_mm_destroy to disable hub intr and de-allocate shadow fault buf that is used to copy mmu fault info during mmu fault handling -implement mm ops remove_bar2_vm This will also unmap and free fault buffers mapped in BAR2 if fault buffers were allocated JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1492682 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: fbhub: num_ltcs are read onlyseshendra Gadagottu2017-06-21
| | | | | | | | | | | | | | | | In gv11b fbhub num_ltcs is read only, even though register spec says it is rw. The number of ltcs are populated by hw and no need for sw to set those values. GPUT19X-70 Change-Id: Ib9861894cacb70cf54b4958083e55d39a3a85e19 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1497992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: ltc reset seqeunce changeseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | Access ltc registers only after bringing ltc out reset. Earlier ltc bought out of reset in fb_reset which is later than accessing ltc registers. GPUT19X-70 Change-Id: Id3b0ac4ed8787a994b7a5848598e4989154a0940 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1495167 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: move cbc init to mmu from ltcseshendra Gadagottu2017-06-07
| | | | | | | | | | | | | | | | | Added cbc_init in fb and removed cbc_init from ltc. Also avoid writing into read only registers in ltc. GPUT19X-70 GPUT19X-116 Change-Id: Ife53e8ec7f049d666baacea3b7c45179e3e13ff9 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1484525 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: add chip specific ECC countersDavid Nieto2017-06-04
| | | | | | | | | | | | | Add support for ECC counters for HUB MMU JIRA: GPUT19X-82 Change-Id: I691d5898d4db9fe2cd68f217baa646479ab5cb00 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1490825 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set only valid soc creditsseshendra Gadagottu2017-06-01
| | | | | | | | | | | | | | | | | | | | | | | Only for following instances, mssnvlink <-> hshub will be interacting in gv11b: NV_ADDRESS_MAP_MSS_NVLINK_1_BASE NV_ADDRESS_MAP_MSS_NVLINK_2_BASE  NV_ADDRESS_MAP_MSS_NVLINK_3_BASE NV_ADDRESS_MAP_MSS_NVLINK_4_BASE   NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub, so don't set those credits. GPUT19X-116 Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1493641 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: Update nvlink soc ceditsseshendra Gadagottu2017-05-29
| | | | | | | | | | | | This temp fix will be modified to call proper nvlink module API, once it is available. Change-Id: Id6e9651452a7d7072c285ab00330c85928cdf4d6 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1489068 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: MMU parity HWW error intrDavid Nieto2017-05-11
| | | | | | | | | | | | | | | | | Adding support for ISR handling of ecc uncorrectable errors for volta resiliency (Volta-686) TODO: move interrupt init out of MC bug 1881052 JIRA: GPUT19X-82 Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1476603 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: set soc credits after fs_hub is out of resetSeema Khowala2017-04-18
| | | | | | | | | | | | Without these credits, gpu mmu binds over nvlink to soc are hanging. Also add l2_enabled for mc_elpg_enable. Bug 1899460 Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1463204 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: ngpu: gv11b: support hub interruptSeema Khowala2017-03-30
| | | | | | | | | | | | | | Hub interrupt handler will be added later JIRA GPUT19X-7 Change-Id: I892e392c6c1fe7d92795b2cab2301f2e68e787c3 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: bl compressionSeema Khowala2016-10-25
| | | | | | | | | | | | | updated mmu pte kind JIRA GV11B-8 Change-Id: I2baff42e077411a9c72b0d10739f4a45d4bd79a7 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1234567 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: sm priv reg related changesSeshendra Gadagottu2016-04-16
Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 07:00:15 -0400