summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv11b/ce_gv11b.c
Commit message (Collapse)AuthorAge
* gpu: nvgpu: gv11b: init get_num_pce ce opsSeema Khowala2017-07-02
| | | | | | | | | | | | | | | Implement get_num_pce ce ops to get number of physical copy engines. This is required to calculate eng method buffer size JIRA GPUT19X-46 Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1511788 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gv11b: add ce interrupt handlingSeema Khowala2017-07-02
| | | | | | | | | | | | | | | | | | | | | | Added handling for below ce interrupts -INVALID_CONFIG interrupt will be generated if a floorswept PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG registers. This is a fatal error and the LCE will have to be reset to get back to a working state. -MTHD_BUFFER_FAULT interrupt will be triggered if any access to a method buffer during context load or save encounters a fault. This is a fatal interrupt and will require at least the LCE to be reset before operations can start again, if not the entire GPU. JIRA GPUT19X-12 JIRA GPUT19X-46 Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1510298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gpu: HW header update for VoltaAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | | Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-06-07
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>