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* Revert "Revert: GV11B runlist preemption patches"Seema Khowala2018-07-19
| | | | | | | | | | | | | | | | | | | This reverts commit 0b02c8589dcc507865a8fd398431c45fbda2ba9c. Originally change was reverted as it was making ap_compute test on embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg preempt with runlist preempt during teardown, preempt timeout set to 100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy chips) and not issuing preempt timeout recovery if preempt fails, helped resolve the issue. Bug 200426402 Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762563 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gv11b: Rearrange gr functionVinod G2018-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | Moved gv11b_detect_ecc_enabled_units function from gv11b.c to gr_gv11b.c, as this is being used only in gr_gv11b file. In order to avoid GR code touching fuse registers, as it need to include fuse HW headers in GR code, introduced two fuse HALs which are being called from GR code. is_opt_ecc_enable for checking whether ecc enable bit is set in fuse register and is_opt_feature_overide_disable for checking whether feature override disable bit is set in fuse register. Initialized fuse HAL functions for chips that make use of those HAL functions. JIRA NVGPU-615 Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775564 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB to commonTerje Bergstrom2018-07-12
| | | | | | | | | | | | Move all FB HAL implementations to common/fb. JIRA NVGPU-596 Change-Id: Id4ea09d608f5d6d1b245bddac09ecf1444b8ab30 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769724 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use HAL for calls from MM to FBTerje Bergstrom2018-07-12
| | | | | | | | | | | | | | | | | | | mm_gv11b.c has several direct calls to fb_gv11b.h. Redirect them to go via a HAL. Also make sure the HALs are using parameter with correct signedness and prefix the parameter constants with NVGPU_FB_MMU_. MMU buffer table indices were also defined in fb_gv11b.h, even though the tables themselves are defined in include/nvgpu/mm.h. Move the indices to include/nvgpu/mm.h and prefix them with NVGPU_MM_MMU_. JIRA NVGPU-714 Change-Id: Ieeae7c5664b8f53f8313cfad0a771d14637caa08 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1776131 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Simplify FB hub intr enableTerje Bergstrom2018-07-11
| | | | | | | | | | | | Hard code flags for enabling and disabling FB hub interrupts. JIRA NVGPU-714 Change-Id: I806ef443cb9e27e221d407d633ca91d8fb40d075 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1769853 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Initialize hwpm perfmons (engine_sel)Vaibhav Kachore2018-07-10
| | | | | | | | | | | | | | - For Mode-E ctxsw it is required that engine_sel is set to 0xFFFFFFFF. - Default 0 is a valid signal and causes problems. Bug 2106999 Change-Id: I5cdb4441a8e6d7e8133c31a9e361b54611dd2995 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770755 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: enable HWPM Mode-E context switchVaibhav Kachore2018-07-10
| | | | | | | | | | | | | | | | | | - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move FB MMU query to FB HALTerje Bergstrom2018-07-09
| | | | | | | | | | | | | | Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count instead of reading the number of LTCs from FB. These changes together remove last direct uses of FB registers from GR. JIRA NVGPU-714 Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773076 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gv11b specific BAR2 deinitTerje Bergstrom2018-07-07
| | | | | | | | | | | | | | | | | gp10b and gv11b variants of remove_bar2_vm are now identical, so delete the gv11b version and use only gp10b version. JIRA NVGPU-714 Change-Id: Ie98cb29803358ddcad8aae2cf865f3baeddebfb1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1773007 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: fix active fbpa mask calculationDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | In gr_gv100_get_active_fpba_mask(), we currently use num_fbpas passed by the caller which is usually litter (max possible on h/w) value We should instead read the number of FBPAs from h/w instead of reading litter value Jira NVGPUT-117 Change-Id: I6ecd4db0fd939e1dfebf31d27e0022ae02809399 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1762721 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to invalidate replay mmu faultDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | Add new HAL gops.fb.mmu_invalidate_replay() to invalidate replay mmu fault Use existing API gv11b_fb_mmu_invalidate_replay() to set to this HAL on all Volta chips Bug 2228914 Jira NVGPU-838 Jira NVGPUT-73 Change-Id: I394901857d41499f3ea44023393fe271fb664260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1767970 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106 SEC2 falcon code updateMahantesh Kumbar2018-07-05
| | | | | | | | | | | | | | | | | | - Added prefix gp106_ to sec2_wait_for_halt() & sec2_clear_halt_interrupt_status() for gp106 SEC2 HAL - Made changes to gp106_sec2_wait_for_halt() to read SEC2 falcon mailbox using common falcon mailbox access functions. - Add define for falcon mailbox - These changes are done to reuse gp106 HAL's for GPU_NEXT. Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1755618 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to get offset in gpccs segmentDeepak Nibade2018-07-05
| | | | | | | | | | | | | | | | | | | | | | In gr_gk20a_find_priv_offset_in_buffer() we right now calculate offset of a register in gpccs segment based on register address type Separate out sequence to find offset in gpccs segment and move it to new API gr_gk20a_get_offset_in_gpccs_segment() Introduce new HAL gops.gr.get_offset_in_gpccs_segment() and set above API to this HAL Call HAL from gr_gk20a_find_priv_offset_in_buffer() instead of calling direct API Jira NVGPUT-118 Change-Id: I0df798456cf63e3c3a43131f3c4ca7990b89ede0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761669 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Enable P-State for Gv100Vaikundanathan S2018-06-27
| | | | | | | | | | Bug 200399373 Change-Id: Ia5d7be7cdb5679c867350da515978d156984a6ea Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726914 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Revert: GV11B runlist preemption patchesAlex Waterman2018-06-26
| | | | | | | | | | | | | | | | | | | | This reverts commit 2d397e34a5aafb5feed406a13f3db536eadae5bb. This reverts commit cd6e821cf66837a2c3479e928414007064b9c496. This reverts commit 5cf1eb145fef763f7153e449be60f1a7602e2c81. This reverts commit a8d6f31bde3ccef22ee77023eaff4a62f6f88199. This reverts commit 067ddbc4e4df3f1f756f03e7865c369a46f420aa. This reverts commit 3eede64de058fcb1e39d723dd146bcd5d06c6f43. This reverts commit 1407133b7e1b27a92ee8c116009541904d2ff691. This reverts commit 797dde3e32647df3b616cea67f4defae59d38b3f. Looks like this makes the ap_compute test on embedded-qnx-hv e3550-t194 quite bad. Might also affect ap_resmgr. Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: Ib9f06514d554d1a67993f0f2bd3d180147385e0a Reviewed-on: https://git-master.nvidia.com/r/1761864 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gv11b: enable RMW for gpu atomicsAshish Srivastava2018-06-26
| | | | | | | | | | | | | | | | | | | | | Separate HAL added in gv11b and gv100 for init_gpc_mmu function. In gv11b HAL, RMW is enabled for gpu atomics as default. In gv100 HAL, GPC atomic capability mode will get set based on the FB MMU capability. If GPU is connected through NVLINK then mmu will be set to RMW mode, else it will be in L2 mode. Bug 200390336 Change-Id: I224934f83d1762ec864ef8da7265dd01d86893a0 Signed-off-by: Ashish Srivastava <assrivastava@nvidia.com> Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735137 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: do not poll preempt done if eng intr pendingSeema Khowala2018-06-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | -During polling eng preempt done, reset eng only if eng stall intr is pending. Also stop polling for eng preempt done if eng intr is pending. -Add max retries for pre-si platforms for poll pbdma and eng preempt done polling loops. Bug 2125776 Bug 2108544 Bug 2105322 Bug 2092051 Bug 2048824 Bug 2043838 Bug 2039587 Bug 2028993 Bug 2029245 Bug 2065990 Bug 1945121 Bug 200401707 Bug 200393631 Bug 200327596 Change-Id: I66b07be9647f141bd03801f83e3cda797e88272f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1694137 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: add support for FECS traceVaibhav Kachore2018-06-22
| | | | | | | | | | | | | | | - This patch sets required fecs trace functions to hals. - In gv100, GPU VA needs to programmed in ucode to get FECS trace. Hence, setting this "NVGPU_FECS_TRACE_VA" characteristic to be true. EVLR-2708 Change-Id: I41845a1db8452b8e3fa9d67ecc4cabfac503fd0b Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747269 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add remove_gr_sysfs gpu opNitin Kumbhar2018-06-15
| | | | | | | | | | | | | | | | | | | | | Add remove_gr_sys() op to gpu_ops to reverse steps done in create_gr_sysfs(). Make gv11b_tegra_remove() specific to gv11b instead to properly remove sysfs nodes. This also helps in having gv11b specific remove steps. Also, update platform remove function of dGPU i.e. nvgpu_pci_tegra_remove() to remove sysfs nodes. This adds parity with iGPU platform remove. Bug 1987855 Change-Id: Ibbaffac5c24346709347f86444a951461894354d Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1735987 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: removed linux includes from CSS HALAntony Clince Alex2018-06-15
| | | | | | | | | | | | | | | | | | | - removed inclusion of linux includes. - replaced with nvgpu/*.h's - reformated the function signature of "css_hw_get_pending_snapshot" and "css_hw_get_overflow_status" be global instead of static. - added get_pending_snapshot and get_overflow_status to ops->css. JIRA: VQRM-3699 Change-Id: I177904c263e143b414924c2c28ad6fd3cfd00132 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1732783 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add HALs for mmu_fault setup and infoDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | Add below HALs to setup mmu_fault configuration registers and to read information registers and set them on Volta gops.fb.write_mmu_fault_buffer_lo_hi() gops.fb.write_mmu_fault_buffer_get() gops.fb.write_mmu_fault_buffer_size() gops.fb.write_mmu_fault_status() gops.fb.read_mmu_fault_buffer_get() gops.fb.read_mmu_fault_buffer_put() gops.fb.read_mmu_fault_buffer_size() gops.fb.read_mmu_fault_addr_lo_hi() gops.fb.read_mmu_fault_inst_lo_hi() gops.fb.read_mmu_fault_info() gops.fb.read_mmu_fault_status() Jira NVGPUT-13 Change-Id: Ia99568ff905ada3c035efb4565613576012f5bef Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744063 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpcseshendra Gadagottu2018-06-14
| | | | | | | | | | | | | | For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to allocate/map/commit global context buffersDeepak Nibade2018-06-14
| | | | | | | | | | | | | | | | | | | | | | Add below new HALs to allocate/map/commit global context buffers gops.gr.alloc_global_ctx_buffers() gops.gr.map_global_ctx_buffers() gops.gr.commit_global_ctx_buffers() Set these HALs for all the supported GPUs We right now re-use below APIs to set these HALs gr_gk20a_alloc_global_ctx_buffers() gr_gk20a_map_global_ctx_buffers() gr_gk20a_commit_global_ctx_buffers() Jira NVGPUT-27 Change-Id: I975a54e8d1716af057f982d543787748d35a256e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1743362 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for SW WARTejal Kudav2018-06-14
| | | | | | | | | | | | | | Workaround of setting SAFE_CTR_INIT on NVLINK (WAR for Bug 1888034) is needed only on nvlink 2.0. Add HAL to avoid running the WAR on future chips. Bug 2006692 Change-Id: I85fb90ea5ce7b848946f2c362e7a952787cc1261 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738401 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL to get link_maskTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | VBIOS link_disable_mask should be sufficient to find the connected links. As VBIOS is not updated with correct mask, we parse the DT node where we hardcode the link_id. DT method is not scalable as same DT node is used for different dGPUs connected over PCIE. Remove the DT parsing of link id and use HAL to get link_mask based on the GPU. JIRA NVLINK-162 Change-Id: Idb7b639962928ce48711a0d7fc277c4c324bee91 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738967 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for minion INIT* dlcmdTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | The sequence of INIT* minion dlcmd varies between nvlink 2.0 and 2.2. The order is strict for 2.2. Also there are new dlcmds added to the nvlink bringup sequence. Add HAL to allow sequence update for nvlink 2.2. Old sequence: INITLANEENABLE-> INITDLPL New Sequence: INITDLPL->INITDLPL_TO_CHIPA->INITTL->INITLANEENABLE JIRA NVLINK-176 Change-Id: I49e0a726f56e7d6122ac4cddf0f0e021d16f1926 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1738329 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Multiple WPR supportMahantesh Kumbar2018-06-14
| | | | | | | | | | | | | | | | | | | | | | | | | The WPR will be divided into several sub-WPRs, one for each Falcon and one common for sharing between Falcons which bootstrap falcons - Defined & used flag NVGPU_SUPPORT_MULTIPLE_WPR to know M-WPR support. - Added struct lsfm_sub_wpr to hold subWPR header info - Added struct lsf_shared_sub_wpr_header to hold subWPR info & copied to WPR blob after LSF_WPR_HEADER - Set NVGPU_SUPPORT_MULTIPLE_WPR to false for gp106, gv100 & gv11b. - Added methods to support to multiple WPR support & called by checking flag NVGPU_SUPPORT_MULTIPLE_WPR in ucode blob preparation flow. JIRA NVGPUTU10X / NVGPUT-99 Change-Id: I81d0490158390e79b6841374158805f7a84ee6cb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725369 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Read sublink state when neededTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | | On nvlink 2.2, we poll for sublink substate to be stable before checking sublink primary state. Currently, we read both TX and RX sublink state during set_sublink_mode() irrespective of which sublink mode is changed. This is not correct when we are polling on substate value while getting sublink state. JIRA NVLINK-164 Change-Id: I474705f059dbf41e5fb7e45bef455c33ee21aa95 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734539 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move SW scratch register read to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | SW scratch register is in bus register range. Move query of that register to bus HAL from bios. JIRA NVGPU-588 Change-Id: I69f35af3d5f8da3550eb68fe7d060a3ec48ce275 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730898 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement bus HAL for bar2 bindTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Separate timer from busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting of BAR0_WINDOW to busTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to common code so that pramin_gk20a.[ch] can be deleted. JIRA NVGPU-588 Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730890 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move setting priv interrupt to priv_ringTerje Bergstrom2018-06-14
| | | | | | | | | | | | | Registers to set priv interrupts are in priv_ring, but the code was in bus HAL. Move the code and related HALs to priv_ring instead. JIRA NVGPU-588 Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730889 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: gv100: Fix therm gopsVaikundanathan S2018-06-14
| | | | | | | | | | | | | Fix test crash with therm sw setup by assigning therm limit and alert HAL functions. Bug 200399373 Change-Id: I972b92d949648a9278d3d351a80cc9a68e23cffc Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1703778 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add gops to load pstate functionsVaikundanathan S2018-06-14
| | | | | | | | | | | | | | | Add gops to choose to/not to enable 1. clk_freq_controller 2. pmgr_domain 3. lpwr_pg Bug 200399373 Change-Id: Ie5131f9ea260f777fded8392f24815acef6cfbea Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702216 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu:nvgpu: Add option for split rail supportVaikundanathan S2018-06-14
| | | | | | | | | | | | Add gops to check whether split rail is suported in the chip Bug 200399373 Change-Id: I5e955127e06d1fbc9b3eca0a895afa0a06f39d91 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1702130 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for pll setupTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | Before nvlink 2.2, driver was responsible for setting the NVLink clocks during NVLink initialization. For the purpose of security, NVLink PLL handling is moved to Minion in nvlink 2.2 and driver should stop writing to these registers. JIRA NVLINK-167 Change-Id: I18392a29c322da55053037bfde62c8f74ee75288 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730597 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: nvlink: Add HAL for RXDETTejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | | RXDET is supported only on nvlink 2.2 devices and forward. Add HAL to run RXDET selectively based on chip. RXDET needs to be done after the links are out of reset but before any other link level initialization. minion_send_cmd is also made non-static to support RXDET functionality. JIRA NVLINK-160 Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1729525 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove check to disallow gv100 link0/1Tejal Kudav2018-06-14
| | | | | | | | | | | | | | | | | | On GV100, we could not enable reflck repeater at source of PLL which is shared by link 0/1. So we do not allow link 0 and 1 to be used on GV100. This refclk repeater is present only on GV100. Remove the check as we currently use link3 on GV100 and do not plan to use any other link. JIRA NVLINK-162 Change-Id: I9ffcc0b20d084a208271d2c594ec64b5bafaabfb Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1734538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Fix include path for clockgating headersVinod G2018-05-29
| | | | | | | | | | | | Removed the reference for $NVGPU/drivers/gpu/nvgpu/common from Makefile and fixed the include path for the clockgating headers in HAL files. Change-Id: I34c179866d28c932501b38184ec18d20dce81480 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730759 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move bus HAL to commonTerje Bergstrom2018-05-25
| | | | | | | | | | | Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs to enable/disable hub interruptsDeepak Nibade2018-05-24
| | | | | | | | | | | | | | | | | | Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-21
| | | | | | | | | | | | | | | | As part of the MISRA fixes, moving all the gating_reglist files to common/clock_gating dir, the new directory structure suggested to follow. Removed unused gating_reglist files for gk20a JIRA NVGPU-646 Change-Id: I388855befcf991ee68eeffed10fe9ac456210649 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1722330 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: do not init idle filtersSeema Khowala2018-05-18
| | | | | | | | | | | | | | | | | | | | | gv100 cannot use idle filter values defined for gp106 since values are different. Also gv100 cannot use gv11b idle filter values since prod values are different between gv100 and gv11b. Finally since PROD values match with POR INIT values, there is no need to init idle filters for gv100. Bug 2115080 Change-Id: I9e7cfbde364d993ae04d80af14650739f32345cc Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1724060 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Code updates for MISRA violationsVinod G2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | | | Code related to MC module is updated for handling MISRA violations Rule 10.1: Operands shalln't be an inappropriate essential type. Rule 10.3: Value of expression shalln't be assigned to an object with a narrow essential type. Rule 10.4: Both operands in an operator shall have the same essential type. Rule 14.4: Controlling if statement shall have essentially Boolean type. Rule 15.6: Enclose if() sequences with braces. JIRA NVGPU-646 JIRA NVGPU-659 JIRA NVGPU-671 Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1720926 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HALs for devinit and preos bios operationsDeepak Nibade2018-05-18
| | | | | | | | | | | | | | | | | | | | | | | Add below new HALs for bios operations gops.bios.devinit() gops.bios.preos() gops.bios.verify_devinit() Export existing APIs gp106_bios_devinit() and gp106_bios_preos() and set them to above HALs on gp106 and gv100 And call new HALs from gp106_bios_init() if supported instead of directly calling APIs Jira NVGPUT-48 Change-Id: Ic89f1c86cf6e3e0785b3663fe733b201d6f2f773 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1708382 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Update gv100 nvlink TLC buffer configTejal Kudav2018-05-18
| | | | | | | | | | | | | | | | | | TLC buffer sizes and credit init values do not match with the values recommended by IAS for dGPU-Xavier configuration. These buffer configuration values affect the latency over link. JIRA NVLINK-158 Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1686601 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv100: use new MINION ucode formatAdeel Raza2018-05-16
| | | | | | | | | | | | | | | | Migrate to the new NVLINK MINION ucode format. The new format strips out an unnecessary ACR header from the ucode image. Moving to the new format will allow MINION ucode generation scripts to be unified. Bug 2113404 Change-Id: I9a72d6c3fa5edd50a4ec5eb835d157672931f994 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1709986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: implement new host semaphore methods for VoltaDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Semaphore methods currently being used in Volta are deprecated for future chips And on Volta we support both old and new methods So replace old methods by new methods on Volta itself so that new methods get tested on silicon Implement below HALs for Volta with new semaphore methods gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Also use new methods in these APIs gv11b_fifo_add_syncpt_wait_cmd() gv11b_fifo_add_syncpt_incr_cmd() And change corresponding APIs to reflect correct size of command buffer gv11b_fifo_get_syncpt_wait_cmd_size() gv11b_fifo_get_syncpt_incr_cmd_size() Jira NVGPUT-16 Change-Id: Ia3a37cd0560ddb54761dfea9bd28c4384cd8a11c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704518 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add HAL to insert semaphore commandsDeepak Nibade2018-05-16
| | | | | | | | | | | | | | | | | | | | | Add below new HALs gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/ release sequence and set it to gops.fifo.add_sema_cmd() Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size() to return respective command buffer sizes Jira NVGPUT-16 Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704490 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 15:54:35 -0400