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* gpu: nvgpu: gp10b: Implement SW methodsTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654098
* gpu: nvgpu: gp10b: Calc global context buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | In gp10b we need to limit global context buffer size, and it needs to be 128b aligned. Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657911 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Add new supported kindTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Define pagepool sizeTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606932 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Define physical address widthTerje Bergstrom2016-12-27
| | | | | | | | | | | | GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601703
* gpu: nvgpu: Write ZBC registers to DSSTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601108
* gpu: nvgpu: Define gp10b big page sizeTerje Bergstrom2016-12-27
| | | | | | | | | | Set default big page size of 128kB. Bug 1567274 Change-Id: Ie27c6ffa23b8d75ebd21afca267068604fb57f0b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/603498
* gpu: nvgpu: Add SM registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | Add SM registers which were taken into use in GPU characteristics. Bug 1551769 Bug 1558186 Change-Id: I705da9ac25556b6b94137199e0acd9af3c8e6422 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601020
* gpu: nvgpu: Use queried interrupt idsTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I258b54447d09b32adc076de50997d792f0567af5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601019 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Implement L2 queryTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: headers for linsim CL 33823014Adeel Raza2016-12-27
| | | | | | | | | Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/594681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable interrupts in linsimTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I7d4211743793b905a20080bb44c62c036f23c854 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592336 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Fill class numbersTerje Bergstrom2016-12-27
| | | | | | | | | | | Fill class numbers to characteristics structure. Bug 1567274 Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594404 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Add own platform data to enable host1xTerje Bergstrom2016-12-27
| | | | | | | | | | | Add gp10b platform data to enable sync point support. Bug 1572701 Change-Id: Iaf03ecb8fb6b8bf4bb824e2a012c80dfe3f4fcae Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592099 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Add SM debug registersTerje Bergstrom2016-12-27
| | | | | | | | | | Add SM debug registers to gp10b, and regenerate headers. Bug 1567274 Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592646
* gpu: nvgpu: gp10b specific CB callbacksTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1570662 Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592101 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement gp10b intr processingTerje Bergstrom2016-12-27
| | | | | | | | | | Bug 1567274 Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/591628 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: t18x, gp10b frameworkKenneth Adams2016-12-27
| | | | | | | | | | | This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams <kadams@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Synchronize gp10b headers with gm20bTerje Bergstrom2016-12-27
| | | | | | | | | | | | Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: headers for linsim CL 33759297Adeel Raza2016-12-27
| | | | | Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5 Signed-off-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: headers for linsim CL 33688874Adeel Raza2016-12-27
| | | | | | | | | | Bug 1561645 Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/553151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: gp10b headersKen Adams2016-12-27
first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/447753
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-24 16:30:27 -0400