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path: root/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c
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* gpu: nvgpu: add cg and pg functionDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU init sequence changeMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: Fix MISRA 15.6 violationsSrirangan2018-08-27
| | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: Ib5961506b0f95867a57f8c0d7024568785fe7b93 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797332 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse HAL to commonTerje Bergstrom2018-08-20
| | | | | | | | | | | | Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add LDIV slowdown factor in INIT cmd.Deepak Goyal2018-05-09
| | | | | | | | | | | | | | | | PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Correct PMU PG enabled masks.Deepak Goyal2018-03-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU ucode records supported feature list for a particular chip as support mask sent via PMU_PG_PARAM_CMD_GR_INIT_PARAM. It then enables selective feature list through enable mask sent via PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE cmd. Right now only ELPG state machine mask was enabled. Only ELPG state machine was getting executed but other crucial steps in ELPG entry/exit sequence were getting skipped. Bug 200392620. Bug 200296076. Change-Id: I5e1800980990c146c731537290cb7d4c07e937c3 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1665767 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update elpg init seq for gv11b.Deepak Goyal2017-12-08
| | | | | | | | | | | | | | | | This updates register address/value pairs for ELPG init sequence in GV11B. Bug 200365505. Change-Id: I62517c378c39f5025f797cf849f10e6b0eae27a8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612642 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: remove GR falcons bootstrap support using VAMahantesh Kumbar2017-10-03
| | | | | | | | | | | | | | | | | | | | - GR falcons bootstrap can be done using physical or virtual address by setting flag usevamask in PMU interface PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS command - With this change always setting to physical address support & removed virtual address support along with code removal. - Removed Linux specific code used to get info regarding WPR VA. JIRA NVGPU-128 Change-Id: Id58f3ddc4418d61126f2a4eacb50713d278c10a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1572468 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg pmu HAL initializationSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8839ac99e87153637005e23b3013237f57275c54 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530982 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move non-fp pmu members from gpu_opsSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move non-function pointer members out of the pmu and pmu_ver substructs of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to g.pmu_ver_cmd_id_zbc_table_update - g.ops.pmu.lspmuwprinitdone has been changed to g.pmu_lsf_pmu_wpr_init_done - g.ops.pmu.lsfloadedfalconid has been changed to g.pmu_lsf_loaded_falcon_id Boolean flags have been implemented using the enabled.h API - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to common flag NVGPU_PMU_ZBC_SAVE - g.ops.pmu.fecsbootstrapdone moved to common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE Jira NVGPU-74 Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530981 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add struct gk20a ptr to FUSE APIsAlex Waterman2017-08-14
| | | | | | | | | | | | | | | | | | | Add a pointer to struct gk20a to the FUSE APIs. This helps QNX builds avoid any static data definitions. Also this change plumbs struct gk20a in some of the Linux clk code and fixes a few minor style nits. Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove privsecurity flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: PMU reset reorgMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | | | | | | | | | | | - nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_copy_from_dmem()Mahantesh Kumbar2017-06-27
| | | | | | | | | | | | | | - replace usage of pmu_copy_from_dmem() with nvgpu_flcn_copy_from_dmem() - delete nvgpu_flcn_copy_from_dmem() JIRA NVGPU-99 Change-Id: If0919187078f95a165d6a152f180549ac121beaa Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1506534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move sysfs dependencies from HAL to LinuxTerje Bergstrom2017-06-27
| | | | | | | | | | | | | Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At the same time the gk20a and gp10b variants are merged into one. JIRA NVGPU-48 Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1466055 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Remove FECS override sysfs APITerje Bergstrom2017-06-27
| | | | | | | | | | | FECS override PMU support was removed with http://git-master/1297370. Remove the sysfs API that is wired to that. Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_* interfacesMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | - set nvgpu_flcn_reset() to point to gk20a_pmu_reset() - set PMU interrupt using nvgpu_flcn_enable_irq() - replace pmu_idle with nvgpu_flcn_wait_idle() JIRA NVGPU-57 Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469478 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>Deepak Nibade2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | Remove <soc/tegra/fuse.h> includes and include <nvgpu/fuse.h> header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: reorganize PMU initMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | - Moved PMU init code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Moved below related methods SW/HW init, init msg handler, deinit/destroy, PMU state machine -Created HAL methods to read message queue tail & supported mutex count. -prepend with nvgpu_ for pmu init global mehtods JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480002 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU IPCMahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | | | | | | - Moved PMU IPC related code to drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file, -Below is the list which are moved seq mutex queue cmd/msg post & process event handling NVGPU-56 Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1478167 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: moved & renamed "struct pmu_gk20a"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | | | | | | | | | - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Use new delay APIsTerje Bergstrom2017-04-13
| | | | | | | | | | | | | | | Use platform agnostic delay functions instead of Linux kernel APIs. This allows removing dependency to Linux header linux/delay.h. At the same time remove #include lines for other unused Linux headers. JIRA NVGPU-16 Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1460114 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gp10b: Use new error macrosTerje Bergstrom2017-04-10
| | | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8dc0ddf3b6ea38af6300c27558b60786c163da6d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457344 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* nvgpu: gpu: pmu: Use pmu ops to call pmu_reset().Deepak Goyal2017-02-24
| | | | | | | | | | | In this patch hard coded function calls for PMU reset are replaced by PMU ops. Change-Id: I266c43e3540163a133895244dcf91169116812f5 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1303757 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use common nvgpu mutex/spinlock APIsDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Delete PMU fecs override interfaceMahantesh Kumbar2017-02-09
| | | | | | | | | | | | | | | | | | Deleted PMU fecs override interface from pmu_api.h header file as feature not used anymore & its dependent code too. Deleted file pmu_api.h as file dont have any interfaces left inside Jira NVGPU-19 Change-Id: I490cf67ae60ce2f1de37da063199ee04835b940d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297370 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: gp10b: Use gops to call pmu_bootstrap().Deepak Goyal2017-01-18
| | | | | | | | | | | | | gops should be used to call non-secure pmu boot functions instead of using direct func() names. JIRA GV11B-30 Change-Id: I27da3b84b61eb978965ae9325ba58e2d02bc6ede Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1282552 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PG statistics updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | - PG statistics read support for multiple engines JIRA DNVGPU-71 Change-Id: I2dc3aad243300d21dc3d20a54a5e4736977e071b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1250507 (cherry picked from commit 985cb3be1d6d990bc6651e417d9e6ba9bfe306e0) Reviewed-on: http://git-master/r/1270991 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPPG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Added rppg module to init GR/MS-RPPG. mscg is dependent on gr-rppg & without gr-rppg engage mscg does not engage. - Update pg engines HAL to return supported pg engines & its sub features JIRA DNVGPU-71 Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247486 (cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9) Reviewed-on: http://git-master/r/1270762 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: update pg engine init/list/features HALMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - Updated gp10b_pg_gr_init() to post init param based on PG engine parameter - Assigned pg engine list/features HAL to respective functions/NULL JIRA DNVGPU-71 Change-Id: I7d059796746694b22800c6ae0327cbc90331e929 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247407 (cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502) Reviewed-on: http://git-master/r/1269321 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: pmu HAL updateseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | Update pmu HAL to have function for is_pmu_supported. JIRA GV11B-21 Change-Id: Id08efa82aa04a6f92c7fea0eb5d4735db2699b5a Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1243918 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: change the usage of tegra_fuse_readlShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Add Fuse prints on PMU HaltSupriya2016-12-27
| | | | | | | | | | | | | | -Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: Icb9677ca278bd316232e07f1d92980f6deb17125 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1120988 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Force GPCCS priv loadTerje Bergstrom2016-12-27
| | | | | | | | | | | | Use priv load for GPCCS instead of DMA. Bug 200204675 Change-Id: Ic7ea7d9e0ef98330e0bdd7606284b8fb3c5bfec8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1155281 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
* gpu: nvgpu: secure boot HAL updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | -And also enable GPCCS load using DMA Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: Id4546fa74954ba7be7c4544d74ad2b7a31b0ecec Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1151788 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use gk20a version of PMU resetTerje Bergstrom2016-12-27
| | | | | | | | | Change-Id: I9b6c2e3bcae4ac43a20089e05891654654df1b54 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150541 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: ECC overrideSupriya2016-12-27
| | | | | | | | | | | | | | | | -sysfs functions to call into LS PMU and modify ECC overide register Bug 1699676 Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/921252 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: clean-up pmu init operationsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Removed unwanted initlization of function pointer. Bug 200157852 Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/843218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ELPG prod values updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | Bug 200151348 Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/836877 (cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193) Reviewed-on: http://git-master/r/837228 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:03:05 -0400