| Commit message (Collapse) | Author | Age |
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Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525713
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.
JIRA NVGPU-93
Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.
- Created ops to do PMU engine reset & to
know the engine reset status
- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)
- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.
JIRA NVGPU-99
Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- replace usage of pmu_copy_from_dmem() with
nvgpu_flcn_copy_from_dmem()
- delete nvgpu_flcn_copy_from_dmem()
JIRA NVGPU-99
Change-Id: If0919187078f95a165d6a152f180549ac121beaa
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1506534
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move sysfs dependencies from gk20a/ and gp10b/ to common/linux. At
the same time the gk20a and gp10b variants are merged into one.
JIRA NVGPU-48
Change-Id: I212be8f1beb8d20a57de04a57513e8fa0e2e83b4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1466055
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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FECS override PMU support was removed with http://git-master/1297370.
Remove the sysfs API that is wired to that.
Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507934
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- set nvgpu_flcn_reset() to point to gk20a_pmu_reset()
- set PMU interrupt using nvgpu_flcn_enable_irq()
- replace pmu_idle with nvgpu_flcn_wait_idle()
JIRA NVGPU-57
Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header
Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()
Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now
Jira NVGPU-75
Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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- Moved PMU init code from pmu_gk20a.c to
"drivers/gpu/nvgpu/common/pmu/pmu.c" file
- Moved below related methods
SW/HW init,
init msg handler,
deinit/destroy,
PMU state machine
-Created HAL methods to read message queue tail
& supported mutex count.
-prepend with nvgpu_ for pmu init global
mehtods
JIRA NVGPU-56
JIRA NVGPU-92
Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1480002
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Moved PMU IPC related code to
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file,
-Below is the list which are moved
seq
mutex
queue
cmd/msg post & process
event handling
NVGPU-56
Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1478167
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved
to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/"
- Included header file "pmu.h" to dependent file &
removed "pmu_gk20a.h" include if its usage is not present.
- Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent
source & header files.
JIRA NVGPU-56
Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1479209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460114
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: I8dc0ddf3b6ea38af6300c27558b60786c163da6d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457344
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
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In this patch hard coded function calls for PMU
reset are replaced by PMU ops.
Change-Id: I266c43e3540163a133895244dcf91169116812f5
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303757
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Deleted PMU fecs override interface from pmu_api.h
header file as feature not used anymore
& its dependent code too.
Deleted file pmu_api.h as file dont
have any interfaces left inside
Jira NVGPU-19
Change-Id: I490cf67ae60ce2f1de37da063199ee04835b940d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1297370
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The fuse headers are unified and moved all the content of
linux/tegra-fuse.h to the soc/tegra/fuse.h to have the
single fuse header for Tegra.
Use unified fuse header soc/tegra/fuse.h.
bug 200260692
Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/1287498
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gops should be used to call non-secure pmu boot
functions instead of using direct func() names.
JIRA GV11B-30
Change-Id: I27da3b84b61eb978965ae9325ba58e2d02bc6ede
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1282552
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.
JIRA GV11B-30
Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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HAL to query LPWR feautre's RPPG/MSCG support
based on current pstate configured.
JIRA DNVGPU-71
Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1283916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move the gp10b HW headers to a new directory specially for them:
include/nvgpu/hw/gp10b
And change the code to include like so:
#include <nvgpu/hw/gp10b/hw_fb_gp10b.h>
This is part of the process to restructure the nvgpu driver.
Bug 1799159
Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280326
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added struct pmu_pg_stats_data to extract
data from multiple version of pmu pg statistics
- Added pmu_pg_stats_v2 interface to fetch
PG statistics data from PMU
- Added MSCG debugfs node to read mscg
statistics from PMU.
- Added pmu_elpg_statistics HAL support for
gp106 PG statistics read.
- Made changes to gp104/gp106
pmu_elpg_statistics HAL to support
for struct pmu_pg_stats_data
JIRA DNVGPU-165
Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252798
(cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd)
Reviewed-on: http://git-master/r/1271615
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- PG statistics read support for multiple engines
JIRA DNVGPU-71
Change-Id: I2dc3aad243300d21dc3d20a54a5e4736977e071b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1250507
(cherry picked from commit 985cb3be1d6d990bc6651e417d9e6ba9bfe306e0)
Reviewed-on: http://git-master/r/1270991
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Updated gp10b_pg_gr_init() to post init param based
on PG engine parameter
- Assigned pg engine list/features HAL to respective
functions/NULL
JIRA DNVGPU-71
Change-Id: I7d059796746694b22800c6ae0327cbc90331e929
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247407
(cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502)
Reviewed-on: http://git-master/r/1269321
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Update pmu HAL to have function for
is_pmu_supported.
JIRA GV11B-21
Change-Id: Id08efa82aa04a6f92c7fea0eb5d4735db2699b5a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1243918
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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tegra_fuse_readl() prototype is changed to match upstreamed
fuse driver, so change implementation accordingly.
Bug 200233653
Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1217376
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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-Print fuse values in case of PMU halt error
-and mailbox reads 0xDEADDEAD
Bug 1737044
Change-Id: Icb9677ca278bd316232e07f1d92980f6deb17125
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/1120988
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Use priv load for GPCCS instead of DMA.
Bug 200204675
Change-Id: Ic7ea7d9e0ef98330e0bdd7606284b8fb3c5bfec8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1155281
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
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-And also enable GPCCS load using DMA
Updated/added secure boot HAL with methods
required to support multiple GPU chips.
JIRA DNVGPU-10
Change-Id: Id4546fa74954ba7be7c4544d74ad2b7a31b0ecec
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1151788
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change-Id: I9b6c2e3bcae4ac43a20089e05891654654df1b54
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1150541
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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-sysfs functions to call into LS PMU and modify
ECC overide register
Bug 1699676
Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/921252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Removed unwanted initlization of function pointer.
Bug 200157852
Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/843218
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 200151348
Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/836877
(cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193)
Reviewed-on: http://git-master/r/837228
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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call gp10b_init_pmu_setup_hw1 during non-secure boot only.
Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/815843
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Modify gpmu hwinit to take gp10b specific register offsets in
non-secure GPMU boot path.
Bug 1685722
Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812271
(cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e)
Reviewed-on: http://git-master/r/813979
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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fix below sparse warning
drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol
'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static?
Bug 200088648
Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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- Required init param to start elpg
- change in statistics dump
Bug 1684939
Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/802455
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/806194
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix below sparse warning by declaring gp10b_write_dmatrfbase()
as static
kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol
'gp10b_write_dmatrfbase' was not declared. Should it be static?
Bug 200088648
Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/801213
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Must write DMATRFBASE1 to 0 whenever
DMATRFBASE is written.
Bug 200137618
Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798780
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- clear mask to load gpcss with priv load.
Bug n/a
Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798406
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1667322
Accomodate for transcfg address change
Change-Id: I83c5d4921040258a480df44a69792c721ff88f05
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/779764
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed the following sparse warning by making the local function as static:
- symbol 'gp10b_pmu_load_multiple_falcons' was not declared.
Should it be static?
- symbol 'gp10b_load_falcon_ucode' was not declared.
Should it be static?
bug 200067946
Change-Id: I67d865aef6f57bf614db351929cd4bb1b6077c00
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/764646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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bug 200080684
Change-Id: I013a0ca7762f6cca0498bd282303597bf683cb7d
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/746737
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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bug 200080684
Change-Id: I5888939017877a50b9bd596393ee8ad1547c18e5
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/732535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added final elpg sequencing value
- by default elpg is disabled.
Bug 1525971
Change-Id: I2c306d9f03e361560a95fcfa723eafe14d004191
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732574
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-method gm20b_pmu_init_acr() used for gp10b
acr init wpr region
Bug 200085428
Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/732213
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Temporally used gm20b elpg sequencing values for gp10b elpg.
Bug 1525971
Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/662517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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