| Commit message (Collapse) | Author | Age |
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In gp10b_round_clk_rate(), we currently call
clk_round_rate() to round the clock rate for us
But since the frequency table is prepared
using the frequency values supported in h/w,
we can round the rate locally using the table
Bug 1827281
Change-Id: I85d034326539590352badceb4164aa5d89ee8842
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1280630
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We right now get min and max frequencies, and then
interpolate rest of the frequencies.
With this approach, we do not select exact
frequencies as supported by h/w
Fix this so that we query all supported frequencies
using clk_round_rate() and then select every N'th
frequency to keep number of frequencies under limit
Use GP10B_FREQ_SELECT_STEP (currently set to 8)
to configure frequency selection step
Raise GP10B_MAX_SUPPORTED_FREQS to 200 since h/w
supported frequencies could be in that range
Bug 1827281
Change-Id: Id8678d7a0280a249e4affbba084ff2e33b6694e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1280629
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent
such problems from occuring in future.
Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GPU frequencies can be set by powerhal when GPU is railgated,
and before this change that would cause EMC floors to remain
set until GPU is unrailgated.
After this change, EMC floors are not requested by the GPU
client when the GPU is railgated. It is ok to ignore the
requests, as the GPU client maxes the floor when powering
up.
Bug 1807560
Change-Id: I9a0d58b0288edbd03b2edf09580ecabd9b74f0c2
Signed-off-by: Juha Lainema <jlainema@nvidia.com>
Reviewed-on: http://git-master/r/1216233
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Cyril Raju <craju@nvidia.com>
Tested-by: Cyril Raju <craju@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Check for is_fmodel instead of check
for simualtion platforms.
Bug 1735760
Change-Id: I14e349088e9414a73353a94613fa031e63bfa31f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177200
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Added control flag for nvgpu infra to allow kernel to create privileged
CE channels for page migration and clearing support between sysmem
and videmem.
JIRA DNVGPU-53
Change-Id: I1fc35eea60af3d1ea9a0b5582011f20d58958ccb
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1173091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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NvGPU is moving to use runtime PM only for its power
management
Remove pm_domain calls to register to nvhost
Jira DNVGPU-57
Change-Id: Idd01b680af0e8fd601801150fc663afa53b7ce6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1163217
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add QoS notifier callback gk20a_scale_qos_notify()
for T186. This enables QoS for T186.
Bug 1772462
Change-Id: Ie25ff4ba24c94354e08fa019704f5d5cc4ef8f33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1161162
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 39a62cba57b243632be56e155813b7318e22c273.
Proper fixes are merged for failing tests.
Hence re-enable railgating
Bug 200198908
Change-Id: Ic9693736add36e7ff77d39fed585126bb6281677
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1163167
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This is done to mask a race issue seen where power refcount
is zero during ISR or bottom half.
Bug 200198908
Change-Id: I0a8ed774cd4fda9db65429b5aad03c5e001ff666
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/1162314
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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This reverts commit fe3adf3d0a72f936788b98365557783b53ecb6ed.
This revert is fixing the Vulkan 1.0.1 CTS failures.
Bug 200196104
Change-Id: I8cc90ac9dc3d29a08341f37e83277a0b431e2187
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/1161577
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Removed platform data parameter clockgate_delay, since it is not
really used for gpu clock gating any more.
Change-Id: I4c7148c70699cb5ed24f0b034ddc92bfb4b41887
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1159594
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set emc floor frequency as zero during rail-gate and set max emc
frequency as floor frequency during rail-ungate.
Bug 1770241
Change-Id: Ib6b6ea6c8b04518423126c3ca3600b4afac15180
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1152848
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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set can_elpg to true to support ELPG init
Bug N/A
Change-Id: I9bdf264689440ef715cf34a5332d03cb60c5aef7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1152432
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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All dynamically allocated sysfs attributes MUST be initialized
explicitly. Otherwise lock debugging fails.
Change-Id: I8f77857831221b5ceddb43f9d161c3bf4ca049d6
Signed-off-by: Remi Denis-Courmont <remid@nvidia.com>
Reviewed-on: http://git-master/r/1145929
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
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For gp10b, set platform data for soc memory aperture type
as vidmem.
Bug 1749338
Change-Id: I7961734d3ebcca4af459c7c7d49bc31f0fc8ce5d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1129168
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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Register debug dump callback gk20a_debug_dump_device()
to nvhost using nvhost_register_dump_device()
Unregister the callback in gp10b_tegra_remove()
Bug 200188753
Change-Id: I9161cfdf969208bd8b6160742bf89e327aa2a6b4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1126792
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gp10b_tegra_scale_init(), return immediately
if CONFIG_GK20A_DEVFREQ is disabled and
profile is NULL
Change-Id: I08e15afdc72bef62a4fb43f30b74cebf8a4b0d68
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1125444
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Use struct device instead of struct platform_device wherever
possible. This allows adding other bus types later.
Change-Id: I90623c020919ca8e2e5b31d53914c324d2dc6af9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120464
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Since gpu rail gating is enabled, force_reset in
idle can be disabled.
Bug 200183798
Change-Id: I04ed04b66e3059459ec32cbffbfdb6756b009200
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1120147
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use Bandwidth manager API to request required
emc clock.
Bug 1673672
Change-Id: I909213d2a69a45939247fd079b1c57ce93be6e0e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/843777
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The ECC sysfs stat creation function is called on GR init. GR can get
initialized multiple times but we only need to create the ECC stats
once. Therefore, add a check to avoid creating duplicate stat sysfs
nodes.
Change-Id: Ifb338e57643f2f15492df137d2a7521e0c990cf2
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1021660
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fixed the following sparse warning by making local symbol static:
- platform_gp10b_tegra.c:365: warning: symbol 'ecc_hash_table' was not declared.
Should it be static?
Bug 200088648
Change-Id: Iea1a682c3ee0609730366d44fab91849cd59c9ad
Signed-off-by: Amit Sharma <amisharma@nvidia.com>
Reviewed-on: http://git-master/r/1022410
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Tested-by: Sachin Nikam <snikam@nvidia.com>
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This reverts commit 7c1f6f0b2998c354f315b431e00f3c8f861cb190.
Bug 200176691
Change-Id: Ia546513ec5c61999f6eb4d56ccd7e45ae072167c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1020813
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-sysfs functions to call into LS PMU and modify
ECC overide register
Bug 1699676
Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/921252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 71b59d75fc49e2159830026bce387ef4d829faa8
since it causes suspend_sanity to fail on quill platform.
On system resume, we see the following error dump from GPU
gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 501 timed out
gk20a 17000000.gp10b: gk20a_fifo_set_ctx_mmu_error_ch: channel 501 generated a mmu fault
gk20a 17000000.gp10b: gk20a_set_error_notifier: error notifier set to 31 for ch 501
gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 509 timed out
Change-Id: I61bc3b0745fe136675ab79b13f54e9126602f51c
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/1017967
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Bug 1698618
Change-Id: Iabfd726891165d7879376ab96445b7b81b907153
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/841856
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ELPG is enabled on TOT.
Bug 200144583
Change-Id: Icbdcb5f575a4ca37becf47b098fbd6a1f89feec7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1013845
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add sysfs nodes for querying ECC single/double bit error counts.
Bug 1699676
Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable engine level power gating(elpg)
Bug 200144583
Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818637
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Make gp10b_freq_table static to fix sparse warning
Bug 200088648
Change-Id: Ibaaabd145e37685e049ac3a49e2b276fb6545d0e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/837421
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for gp10b freq scaling.
Bug 200147662
Reviewed-on: http://git-master/r/816962
(cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438)
Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set initial gpcclk rate to 1GHz.
Bug 200151332
Reviewed-on: http://git-master/r/834113
(cherry picked from commit 9ed69164da7afeec20c3a557885f74db4cbea9cb)
Change-Id: I85107eb5852b25977b30663f6ae173b271ecafeb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/834322
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2.
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1
Reviewed-on: http://git-master/r/830854
GVS: Gerrit_Virtual_Submit
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Set platform data with ptimer source frequency.
Removed ptimerscaling10x platform data, and use
ptimer source frequency to calculate ptimerscaling
factor.
Reviewed-on: http://git-master/r/819031
(cherry picked from commit 6849603024943184b0463233bedd95934c353663)
Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/827301
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Enable clock gating power features: slcg, blcg and elcg
Bug 200144583
Reviewed-on: http://git-master/r/821149
(cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce)
Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/818636
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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set platform specific channel watchdog timeout to 5s
for gp10b
Bug 200133289
Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/811509
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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The powergating APIs only work if the BPMP is running. Skip
these calls if it's not available, instead of relying on
is_linsim, which doesn't work under all environments.
Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/812415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1688709
Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/807030
(cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1)
Reviewed-on: http://git-master/r/808243
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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bug 1603226
t18x fixes ptimer bug and ticks at 1ns.
Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/799989
(cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1)
Reviewed-on: http://git-master/r/707810
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement platform specific reset_assert() and reset_deassert()
calls for gp10b
These APIs will in turn will use reset_control APIs to do
their work
Also, set force_reset_in_do_idle = true for gp10b, since
railgating is not supported yet
Bug 200137963
Change-Id: I2c0fe1273d3ecfd0c46704a44374712052ff51d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797150
(cherry picked from commit 6ac04ca84cee8a4d3b089678c81534799880712d)
Reviewed-on: http://git-master/r/808240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use CCF to enable GPU clocks. Keep an extra reference to prevent
runtime PM callbacks from disabling clocks while GPU is powered up.
Bug 1673672
Change-Id: I8c34be5ec338fedea62aa3e05bd6bed0513bf1b6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/788814
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/785265
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Add debugfs switch to force cilp and gfx preemption
Add debugfs switch to dump context switch stats on channel
destruction.
bug 1525327
bug 1581799
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66
Reviewed-on: http://git-master/r/794976
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677231
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Bug 200086985
Change-Id: I9eaa135b96629636a6b949ae1e3874dd3abd5138
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/794723
Reviewed-on: http://git-master/r/743217
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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VPR allocator needs to be used when allocating graphics context for
VPR channels. Define it for gp10b.
Bug 1625090
Change-Id: Ie2e3a865c310c34c629627891ac0b579f299983f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/737846
Reviewed-by: Automatic_Commit_Validation_User
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Change-Id: I1fcc7e93d3e31bfbb5d540b43b655566f6dc13cd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/732010
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Mark CDE as supported on t18x.
Change-Id: I03c23178712b9018137edddfa8e1ff3a2ad9106c
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/672384
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set default big page size to 64kB.
Bug 1592495
Change-Id: Id23dac012cde75f2809a49779e1a1cee879d08a0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/671705
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Temporally used gm20b elpg sequencing values for gp10b elpg.
Bug 1525971
Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/662517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Set default big page size of 128kB.
Bug 1567274
Change-Id: Ie27c6ffa23b8d75ebd21afca267068604fb57f0b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/603498
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