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* gpu: nvgpu: add get_iova_addr() for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | Add platform specific gp10b_mm_iova_addr() to get iova/phys address for gp10b If SMMU is not enabled and IO coherence flag is set, set 34th bit in the physical address and return the physical address If SMMU is enabled, return the iova address Bug 1605653 Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713106 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use mem_desc for buffersTerje Bergstrom2016-12-27
| | | | | | Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712836
* gpu: nvgpu: gp10b: Use gp10b version of phys bitsTerje Bergstrom2016-12-27
| | | | | | | | Use gp10b version of get_physical_addr_bits. Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/714402
* gpu: nvgpu: gp10b: Add replayable pagefault bufferSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for replayable fault buffer and enable it. Bug 1587836 Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661668 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: setup mm hw initSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add Bar2 supportSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Correct SMMU bit numberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Bit 36 is the correct bit to indicate SMMU translation. Bug 1580756 Change-Id: I761e70265d5981b07940f1d43716416829993827 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/658827 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
* gpu: nvgpu: gp10b: Define physical address widthTerje Bergstrom2016-12-27
GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601703
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 23:13:07 -0400