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* gpu: nvgpu: adapt gk20a_mm_entry for mem_descKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | For upcoming vidmem refactor, replace struct gk20a_mm_entry's contents identical to struct mem_desc, with a struct mem_desc member. This makes it possible to use the page table buffers like the others too. JIRA DNVGPU-23 JIRA DNVGPU-20 Change-Id: Ia82da07b5a3bb9fb14a86bcf96a46b3a3c80bf28 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1139696 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Ken Adams <kadams@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use sysmem aperture for SoC memoryTerje Bergstrom2016-12-27
| | | | | | | | | | | | | In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it has to be accessed as sysmem. Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1122591 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: gp10b: Support GPUs with no physical modeTerje Bergstrom2016-12-27
| | | | | | | | | | | | Support GPUs which cannot choose between SMMU and physical addressing. Change-Id: Ic097fccb313d98fcea918a705eefb5cd619138f1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1122590 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: User-space managed address space support (gp10b)Sami Kiminki2016-12-27
| | | | | | | | | | | | Tell gk20a_init_vm() that bar2 VM is kernel-managed. Bug 200077571 Change-Id: I151c540a6dec76238e7959f745cfca280927f2d4 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/746803 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: gp10b: Implement sparse PDEs"Terje Bergstrom2016-12-27
| | | | | | | | | | | | | This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It introduces regression in T124. Bug 1702063 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b Reviewed-on: http://git-master/r/830787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Implement sparse PDEsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/758653
* gpu: nvgpu: gp10b: support to remove bar2 vmSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Implement function to support bar2 vm clean-up. Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/814573 Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/815428 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix ctag computation overflow with 8GBJussi Rasanen2016-12-27
| | | | | | | | | | | | | Bug 1689976 Change-Id: Ibf1c296fac4f2a2c6fcf062cbd80b3526a4fd4ed Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/806588 (cherry picked from commit 24b57989dc9636b41004bac32ee56dce90318350) Reviewed-on: http://git-master/r/808242 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Separate kernel and user GPU VA regions (gp10b)Sami Kiminki2016-12-27
| | | | | | | | | | | | Specify that everything in bar2 VM is kernel reserved. Bug 200077571 Change-Id: I8f6c6ac6352ffd64eedc09187593b6c8d05757ef Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/746802 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use phys addresses in PDEsTerje Bergstrom2016-12-27
| | | | | | | | | | | | Use physical addresses in PDEs. All page table levels fit in 4k, so no need for SMMU mapping. Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/783748 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* Revert "gpu: nvgpu: gp10b: Phys addresses for page tables"Matt Craighead2016-12-27
| | | | | | | | | | This reverts commit f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5. Change-Id: I0acfa18e9cf9bedd4051ec00faa497b3cdb9454b Signed-off-by: Matt Craighead <mcraighead@nvidia.com> Reviewed-on: http://git-master/r/768599 Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com> Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
* gpu: nvgpu: gp10b: Implement priv pagesTerje Bergstrom2016-12-27
| | | | | | | | Implement support for privileged pages. Use them for kernel allocated buffers. Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/761920
* gpu: nvgpu: gp10b: Phys addresses for page tablesTerje Bergstrom2016-12-27
| | | | | | | | | | | | Use always physical addresses for page tables. In gp10b new format each level fits in one page, so we do not need SMMU translation. Change-Id: Ie46b2bce0f7a4e8d2904d74b1df616e389874141 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/758181 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gp10b: Fix PDE/PTE address handlingTerje Bergstrom2016-12-27
| | | | | | | | | | | | We were dropping the part of address that span word bounary. The register generator does not know how to real with multi-word fields, to edit things in manually. Bug 1646531 Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/747468
* gpu: nvgpu: gp10b: Fix comptag index calculationTerje Bergstrom2016-12-27
| | | | | | | | | | Used 128k comptag spacing, when 64k is the correct one. Bug 1525976 Change-Id: Ie2f926929fa89cf715b86a57ffbf4dd1e4920473 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/737947
* gpu: nvgpu: gp10b: Enable new page table formatTerje Bergstrom2016-12-27
| | | | | | | | | | Enable new page table format for all platforms. Bug 1525976 Change-Id: I9a3cfabdef7dc6ec33e18a8a4f32063c40f680fa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/737364
* gpu: nvgpu: gp10b: Fix caching attributeTerje Bergstrom2016-12-27
| | | | | | | | | | Fix caching attribute on 5-level page tables. Bug 1525976 Change-Id: I5c5bf336d87c642f42a387206a55a889e6e07ba6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/737923
* gpu: nvgpu: gp10b: fix sparse warnings of static symbolDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: I222bebd958e29b3a95d161f05a3052389200fc10 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/736663 GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: gp10b: Make page mapping scatter awareTerje Bergstrom2016-12-27
| | | | | | | | | | | Augment new page mapping code to be aware of scattered buffers. Bug 1605769 Change-Id: Ifdb326563d28ccf07fc4d3d76a24492a68493fe3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/734355
* gpu: nvgpu: gp10b: Implement new page table formatTerje Bergstrom2016-12-27
| | | | | | | | | Implement the 5-level Pascal page table format. It is enabled only for simulation. Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/682114
* gpu: nvgpu: gp10b: fix sparse warnings of static symbolDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: add get_iova_addr() for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | Add platform specific gp10b_mm_iova_addr() to get iova/phys address for gp10b If SMMU is not enabled and IO coherence flag is set, set 34th bit in the physical address and return the physical address If SMMU is enabled, return the iova address Bug 1605653 Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/713106 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Use mem_desc for buffersTerje Bergstrom2016-12-27
| | | | | | Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712836
* gpu: nvgpu: gp10b: Use gp10b version of phys bitsTerje Bergstrom2016-12-27
| | | | | | | | Use gp10b version of get_physical_addr_bits. Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/714402
* gpu: nvgpu: gp10b: Add replayable pagefault bufferSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for replayable fault buffer and enable it. Bug 1587836 Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/661668 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: setup mm hw initSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add Bar2 supportSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Correct SMMU bit numberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Bit 36 is the correct bit to indicate SMMU translation. Bug 1580756 Change-Id: I761e70265d5981b07940f1d43716416829993827 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/658827 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
* gpu: nvgpu: gp10b: Define physical address widthTerje Bergstrom2016-12-27
GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601703
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 11:32:32 -0400