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path: root/drivers/gpu/nvgpu/gp10b/mc_gp10b.h
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* gpu: nvgpu: Split non-stall interrupt handlingTerje Bergstrom2017-06-07
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half worker. It uses the new MC HALs intr_nonstall (query interrupt status), intr_nonstall_pause (pause interrupts), intr_nonstall_resume (resume interrupts), and is_intr1_pending (query per-engine interrupt bit). MC HAL isr_nonstall is removed, because its work is now handled in chip independent code. JIRA NVGPU-26 Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497048 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split stalling interrupt handlingTerje Bergstrom2017-05-26
| | | | | | | | | | | | | | | | | | | | | | Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half. It uses the new MC HALs intr_stall (query interrupt status), intr_pause (pause interrupts) and intr_resume (resume interrupts). MC HAL isr_stall now returns void and gets called in thread context and thus remove isr_thread_stall and replace the implementation with isr_stall. JIRA NVGPU-26 Change-Id: I206f330f6fc4a1f4def47c5f986585ac4080216d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1480243 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Handle MC pmu interruptsMahantesh Kumbar2016-12-27
| | | | | | | | | | - Made changes to MC to get pmu interrrupts Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/661212 Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Implement gp10b intr processingTerje Bergstrom2016-12-27
Bug 1567274 Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/591628 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
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