| Commit message (Collapse) | Author | Age |
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Restore comptags to be bitmap-allocated, like they were before we had
the buddy allocator.
Bug 200145635
Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/839240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Use bindings more specific to the ARM SMMU.
Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/812438
(cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0)
Reviewed-on: http://git-master/r/831515
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
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Compbit backing store did not take into account number of GOBS
per comptagline per slice.
Bug 1604102
Change-Id: I42666e72ea54697b6fbc7318e65a6a09d867f5b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/754706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
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This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85
since the issue seen with bug 200106514 is fixed with change
http://git-master/r/#/c/752080/.
Bug 200112195
Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/752504
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Change for new VA space allocator is being reverted with
http://git-master/r/#/c/749291/ but only for Kernel3.18
In Kernel3.10, we support the new VA allocator
Since we support both the kernel versions as of now,
use a KERNEL_VERSION based mechanism to select
appropriate call
Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10
where we want to use new allocator
Bug 200106514
Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/751353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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This reverts commit 30e5947fa1f26ed6bb4f137fd76c8869e91b9829.
The original commit was actually fine.
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: I0454415981d29ed0b877f7a21db6f54bc4c30470
Reviewed-on: http://git-master/r/743302
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 3a4f0285c7e9212b394b2c1b151987a7084de927.
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I886e434ce98e85f99b0a77749179e31c0bd00620
Reviewed-on: http://git-master/r/741468
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
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The comptag allocator is made in the chip-specific init code
for the comptags. Thus, a t18x change needs to be made to make
sure the new allocator code compiles and works on t18x.
Change-Id: I57a34f3c61ebd31f875caa577378e829812f2d4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/721171
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Program a constant stream id 31 to LTC.
Bug 1610019
Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/724348
Reviewed-by: Automatic_Commit_Validation_User
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Do not clear compbit store size if max size is zero. It's already
zero at this point.
Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/720599
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LTC interrupt register got moved, so use the new offset.
Bug 1587638
Change-Id: I3dbd44d92f2bcb3634c21ed46870ec1620d936cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709571
Reviewed-by: Automatic_Commit_Validation_User
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Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE
during t18x ltc init and store it for use in CDE code.
Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/673150
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Define compression page size for gp10b to be 64k. We also need to
copy some LTC initialization code from gm20b to gp10b.
Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677837
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L2 size is expressed in kB, so add a multiplier.
Bug 1592495
Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/671704
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Bug 1567274
Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/602858
Reviewed-by: Automatic_Commit_Validation_User
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