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path: root/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
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* gpu: nvgpu: gp10b: add ECC stats sysfs nodesAdeel Raza2016-12-27
| | | | | | | | | | | Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC supportAdeel Raza2016-12-27
| | | | | | | | | | | | | Add ECC exception handling support for SM, TEX, and LTC. Bug 1635727 Bug 1637486 Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935362 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Program stream id to LTCTerje Bergstrom2016-12-27
| | | | | | | | | | | Program a constant stream id 31 to LTC. Bug 1610019 Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/724348 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: read gobs_per_comptagline_per_sliceJussi Rasanen2016-12-27
| | | | | | | | | | | | Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE during t18x ltc init and store it for use in CDE code. Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441 Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com> Reviewed-on: http://git-master/r/673150 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement L2 queryTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: headers for linsim CL 33823014Adeel Raza2016-12-27
| | | | | | | | | Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/594681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add SM debug registersTerje Bergstrom2016-12-27
| | | | | | | | | | Add SM debug registers to gp10b, and regenerate headers. Bug 1567274 Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592646
* gpu: nvgpu: Synchronize gp10b headers with gm20bTerje Bergstrom2016-12-27
| | | | | | | | | | | | Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: headers for linsim CL 33759297Adeel Raza2016-12-27
| | | | | Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5 Signed-off-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: headers for linsim CL 33688874Adeel Raza2016-12-27
| | | | | | | | | | Bug 1561645 Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/553151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu: nvgpu: gp10b headersKen Adams2016-12-27
first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/447753
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 06:49:03 -0400