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path: root/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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* gpu: nvgpu: gp10b: Use new error macrosTerje Bergstrom2017-04-10
| | | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8dc0ddf3b6ea38af6300c27558b60786c163da6d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457344 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add wrapper for linux/types.hTerje Bergstrom2017-04-03
| | | | | | | | | | | | | | | | Add wrapper header nvgpu/types.h. It checks if build is for Linux kernel and pulls in linux/types.h. Delete also all #includes for linux/types.h which are not strictly necessary, and change the remaining ones to use the new wrapper. JIRA NVGPU-13 Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1453371 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split out pramin codeAlex Waterman2017-03-31
| | | | | | | | | | | | | Split out the pramin interface code in preparation for splitting out the mem_desc code. JIRA NVGPU-12 Change-Id: I3f03447ea213cc15669b0934fa706e7cb22599b7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323323 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove unnecessary use of dev_name()Terje Bergstrom2017-03-28
| | | | | | | | | | | | | | | Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1328534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: Remove checks for privsec on vgpuTerje Bergstrom2017-03-20
| | | | | | | | | | | | | In virtualized platform we don't have access to fuses. Skip reading fuse and set priv security unconditionally. Change-Id: Idcb2670ed48a5edb760e49a6d136d53e05bc34ef Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323283 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Tested-by: Richard Zhao <rizhao@nvidia.com>
* gpu: nvgpu: Implement get_rate/set_rate as GPU opTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | | | | Move clock APIs from gk20a_platform to gpu_ops. At the same time allow use of internal get_rate/set_rate for querying both GPCCLK and PWRCLK on iGPU. At the same time we can replace calls to clk framework with the new HAL and drop direct dependency to clk framework. gp10b ops were replaced as a whole at HAL initialization. That replaces anything set in platform probe stage, so reduce that to touch only clock gating regs. Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300113 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use GPU's own fuse registersTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | Read fuse values from GPU's own fuse registers instead of Tegra fuse registers whenever possible. This reduces the number of dependencies to Linux fuse code. Some fuses do not have a corresponding register in GPU, so they're left as is. Change-Id: Id9f2f4da897f3e20b20c300a67f705e3fa5ba35a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1318278 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: hardcode gp10b fbpa valuesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | gp10b does not have an fbpa unit, although the hw header files claim it does. Hardcode all fbpa values to 0. Bug 200249125 Change-Id: I6ed63b3231d7af8e31ccf5047d56bdb85f05a9d9 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1256422 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add FBPA base addressesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add FBPA base addresses Bug 200249125 Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1247802 (cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a) Reviewed-on: http://git-master/r/1252163 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: updated API for get_litter_valueseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | get_litter_value API is updated to use int instead of enum type. JIRA GV11B-21 Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1252212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: define fuse macro depend on kernel versionShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | | | - Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4 Bug 200243956 Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245825 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add dGPU clocks supportVijayakumar Subbu2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: change the usage of tegra_fuse_readlShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: vgpu: cyclestat snapshot supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | Add support for cyclestats snapshots in the virtual case Bug 1700143 JIRA EVLR-278 Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1216644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move dbg_session_ops to gopsPeter Daifuku2016-12-27
| | | | | | | | | | | | | | Move dbg_session_ops to gops for better code consistency JIRA VFND-1905 Change-Id: I0ac10a69194c8ca485f361cd8cea61d8ab72145a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1192642 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gp10b: add is_fmodel checkSeema Khowala2016-12-27
| | | | | | | | | | | | | | | | | | Check for is_fmodel instead of check for simualtion platforms. Bug 1735760 Change-Id: I14e349088e9414a73353a94613fa031e63bfa31f Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1177200 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com>
* gpu: nvgpu: ppc register supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | | | | | | Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: Icb0bdedbe78ec4246426789e62302118682ed20a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1189608 Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* Revert "gpu: nvgpu: ppc register support"Hoang Pham2016-12-27
| | | | | | | | | | This reverts commit 3639659575e76f81e31c5c9f3aca8896c4ebcb69. Change-Id: Ieb6a40e30128bb9c59f64f6e39bb026de9a30397 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/1189599 Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com> Tested-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: ppc register supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | | | | Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: I1d04bfd20eac08a26986a2436524b97a008ed913 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1158889 (cherry picked from commit 0f9ac2fd958556ee5d76d4cb2f6a335960227433) Reviewed-on: http://git-master/r/1164398 (cherry picked from commit aa12f60061bdbeb68094d59258ac2db34f0cfe2a) Reviewed-on: http://git-master/r/1181501 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: set gops.read_ptimerRichard Zhao2016-12-27
| | | | | | | | | | | | | Bug 1395833 Change-Id: I7e7f453d83db76a46f79d62f205832254fcf401e Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1159589 (cherry picked from commit a1f43172ebf91066969c4d9e25b8a781edb20724) Reviewed-on: http://git-master/r/1158898 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: init tsg HAL opsRichard Zhao2016-12-27
| | | | | | | | | | | | | Bug 1702773 Change-Id: I9b6e1d0f2f4fe979f6fab83347884bd69413ccda Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144935 (cherry picked from commit f79eb75272879c869b137cd042312db0a5953412) Reviewed-on: http://git-master/r/1127031 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add litter values HALTerje Bergstrom2016-12-27
| | | | | | | | | | | Move per-chip constants to be returned by a chip specific function. Implement get_litter_value() for each chip. Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1121384 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Determine ECC-enabled units for GP10BSami Kiminki2016-12-27
| | | | | | | | | | | | | | | | Determine ECC-enabled units for GP10B by reading fuses/registers. Bug 1637486 Change-Id: I6431709e3c405d6156dd96438df14d4054b48644 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/780992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120463 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvpgu: setup fecs_trace hal operationsThomas Fleury2016-12-27
| | | | | | | | | | bug 1648908 Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update prod setiingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Add/update following prod settings: blcg ce slcg ce2 Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1030986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: update thermal programmingSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | | | | Add required fileds and values for thermal slow-down settings in thermal header file and corrected thermal register programming with correct values. Bug 1695567 Reviewed-on: http://git-master/r/822200 (cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981) Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/823013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Report Pascal DMA copy classTerje Bergstrom2016-12-27
| | | | | | | | | | | | Announce supporting Pascal DMA copy class instead of Maxwell. Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/808140 (cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7) Reviewed-on: http://git-master/r/815679 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: update slcg xbar prod settingsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Bug 1689806 Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/806115 (cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd) Reviewed-on: http://git-master/r/805482 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Always disable security in simTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/801850 Reviewed-on: http://git-master/r/806192
* gpu: nvgpu: fuse read to boot in SECURE modeMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | -Read fuse to boot in secure/production mode else non sercure mode. Bug N/A Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/791323 Reviewed-on: http://git-master/r/806191 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add CDE program number selection for GP10BSami Kiminki2016-12-27
| | | | | | | | | | | Add CDE program number selection for GP10B. Bug 1604102 Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/785459 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add regops whitelistsTerje Bergstrom2016-12-27
| | | | | | | | | | | Add regops whitelists for gp10b. The whitelist is generated, and is the same for context switched and global registers. Bug 1633363 Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/760935
* gpu: nvgpu: gp10b: Do not set up gm20b clocksTerje Bergstrom2016-12-27
| | | | | | | | | | | gm20b clock registers do not exist in gp10b. Skip setting the clock HAL to gm20b variants. Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/760854 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Gating reglistTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/731494
* gpu: nvgpu: secure boot flag, default disabledMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | - set "privsecurity" to 1 to enable secure boot else set to 0. Bug 200085428 Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/729101 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix sparse warnings of static symbolDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: gp10b: support for replayable faultsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ce interrupt supportSam Payne2016-12-27
| | | | | | | | | | | | | ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Set correct PBDMA signatureTerje Bergstrom2016-12-27
| | | | | | | | | GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672921
* gpu: nvgpu: gp10b: Enable debug spewTerje Bergstrom2016-12-27
| | | | | | | Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/679704 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Enable cycling through ctx binsTerje Bergstrom2016-12-27
| | | | | | | | | | | Remove hard coded NETB for gp10b. This enables cycling through available firmware files. Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/676557 Reviewed-by: Peng Du <pdu@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: gpmu elpg supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add new supported kindTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Define physical address widthTerje Bergstrom2016-12-27
| | | | | | | | | | | | GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601703
* gpu: nvgpu: gp10b: Implement L2 queryTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Fill class numbersTerje Bergstrom2016-12-27
| | | | | | | | | | | Fill class numbers to characteristics structure. Bug 1567274 Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594404 Reviewed-by: Automatic_Commit_Validation_User
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-24 09:48:35 -0400