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path: root/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
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* gpu: nvgpu: gp10b: functions made non-staticSeema Khowala2017-06-29
| | | | | | | | | | | | | | gr_gp10b_handle_fecs_error and gr_gp10b_set_cilp_preempt_pending made non-static to be reused for t19x Bug 200289491 Change-Id: I8ef7ffab1209abc7f7d7d05cbbdf8ce4365613c5 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master/r/1505954 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: re-arrange parity countersDavid Nieto2017-05-24
| | | | | | | | | | | | | (1) Re-arrange the structure for parity counters reporting so multiple units can be managed JIRA: GPUT19X-84 Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1485276 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add gr_t19x support for gv11b ECCLakshmanan M2017-05-18
| | | | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added gr_t19x support for gv11b ECC 2) Modified the gp10b platform config for gv11b sysfs support JIRA GPUT19X-85 JIRA GPUT19X-104 JIRA GPUT19X-100 JIRA GPUT19X-103 Bug 1825948 Bug 1825962 Bug 1775457 Change-Id: I0bf13f80a73cc2184147230d098e89a517554c01 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1478952 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename mem_desc to nvgpu_memAlex Waterman2017-04-06
| | | | | | | | | | | | | | | | | Renaming was done with the following command: $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' Also rename mem_desc.[ch] to nvgpu_mem.[ch]. JIRA NVGPU-12 Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1325547 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove circular dependency in PMU includesTerje Bergstrom2017-01-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove including gk20a.h from pmu_gk20a.h. This causes a fallout as some #includes were missing. gr_gp10b.h uses mem_desc, but did not include mm_gk20a.h. Add the include. Including mm_gk20a.h in gr_gp10b.h causes recursive include, as mm_gk20a.h has some gr defines. Move the defines to gr_gk20a.h to remove the dependency. gr_ctx_gk20a.h used struct gk20a pointers, but did not forward declare it. Add a forward declaration. gr_gk20a.h uses dbg_session_gk20a, but was missing forward declaration. gr_gk20a.h did not include nvgpu.h but it uses preemption types from that header. Add include. Change-Id: I2168e2303b55e0d187b816bcb26f37c8af1649ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1283717 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: Implement SET_RD_COALESCETerje Bergstrom2017-01-05
| | | | | | | | | | | | | Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add new CE class for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104. JIRA DNVGPU-25 Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1166709 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Fix CWD floorsweep programmingTerje Bergstrom2016-12-27
| | | | | | | | | | | | Program CWD TPC and SM registers correctly. The old code did not work when there are more than 4 TPCs. Change-Id: I18a14a0f76d97b0962607ec0bbd71aafcd768bca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1143075 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: add code to handle DT fuse overridesAdeel Raza2016-12-27
| | | | | | | | | | | | | | Add code for handling GP10B fuse overrides specified in the device tree. Also add specific handling for the ECC fuse override. Bug 1699676 Change-Id: Ifa07983054cd143f7f1745a6a6de36f4d4e08126 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1140893 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: API to set preemption modeDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate out new API gr_gp10b_set_ctxsw_preemption_mode() which will check requested preemption modes and take appropriate action for each preemption mode This API will also do some sanity checking for valid preemption modes and combinations Define API set_preemption_mode() for gp10b which will set the preemption modes passed as argument and then use gr_gp10b_set_ctxsw_preemption_mode() and update_ctxsw_preemption_mode() to update preemption mode Legacy path from gr_gp10b_alloc_gr_ctx() will convert flags NVGPU_ALLOC_OBJ_FLAGS_* into appropriate preemption modes and then call gr_gp10b_set_ctxsw_preemption_mode() New API set_preemption_mode() will use new flags NVGPU_GRAPHICS/COMPUTE_PREEMPTION_MODE_* and set and update ctxsw preemption mode In gr_gp10b_update_ctxsw_preemption_mode(), update graphics context to set CTA premption mode if mode NVGPU_COMPUTE_PREEMPTION_MODE_CTA is set Also, define preemption modes in nvgpu-t18x.h and use them everywhere Remove old definitions of modes from gr_gp10b.h Bug 1646259 Change-Id: Ib4dc1fb9933b15d32f0122a9e52665b69402df18 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1131806 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pass bool pointer to debugfs_create_bool()Deepak Nibade2016-12-27
| | | | | | | | | | | Port the change 621a5f7ad9cd1ce7933f1d302067cbd58354173c from kernel.org to the nvgpu driver Change-Id: I3a8aa873e1f0b601bfe89f836c400113e50b638e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1125443 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Use device instead of platform_deviceTerje Bergstrom2016-12-27
| | | | | | | | | Use struct device instead of struct platform_device wherever possible. This allows adding other bus types later. Change-Id: I90623c020919ca8e2e5b31d53914c324d2dc6af9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120464
* gpu: nvgpu: gp10b: add ECC stats sysfs nodesAdeel Raza2016-12-27
| | | | | | | | | | | Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add CILP support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheableAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement SetCoalesceBufferSizeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement method for setting the coalesce buffer size at runtime. Bug 1681992 Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/802366 (cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611) Reviewed-on: http://git-master/r/808239 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: add debug features for gfxp and cilpKirill Artamonov2016-12-27
| | | | | | | | | | | | | | | | Add debugfs switch to force cilp and gfx preemption Add debugfs switch to dump context switch stats on channel destruction. bug 1525327 bug 1581799 Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66 Reviewed-on: http://git-master/r/794976 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/677231
* gpu: nvgpu: gp10b: Correct C097_SET_GO_IDLE_TIMEOUT offsetRobert Morell2016-12-27
| | | | | | | | | | | Bug 1678603 Change-Id: I1c2c3c9395e068fabf554779ded6f0f536622c90 Signed-off-by: Robert Morell <rmorell@nvidia.com> Reviewed-on: http://git-master/r/792831 Reviewed-on: http://git-master/r/806187 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Implement NVC0_SET_GO_IDLE_TIMEOUTTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1678603 Change-Id: Ib8fb09dace864567b1ce574c216a584831723684 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/790402 Reviewed-on: http://git-master/r/806185
* gpu: nvgpu: gp10b: Enable CILP mode for computeTerje Bergstrom2016-12-27
| | | | | | | | | | | Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement gp10b context creationTerje Bergstrom2016-12-27
| | | | | | | | | | | Implement context creation for gp10b. GfxP contexts need per channel buffers. Bug 1517461 Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660236
* gpu: nvgpu: gp10b: Implement SW methodsTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654098
* gpu: nvgpu: t18x, gp10b frameworkKenneth Adams2016-12-27
This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams <kadams@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 19:30:33 -0400