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path: root/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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* gpu: nvgpu: Debug spew for context priority & GfxpMihir Thakkar2017-01-24
| | | | | | | | | | | | | | | | Prints out Timeslice value, Interleave level, Graphics preemption mode and compute preempt mode along with chid, tsgid, pid. Enable it with setting dbg_mask with 8192 Bug 1855710 Change-Id: I60efef9810587f8fedd4e2ba62ba67d06d84faea Signed-off-by: Mihir Thakkar <mthakkar@nvidia.com> Reviewed-on: http://git-master/r/1287141 Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gk20a codeAlex Waterman2017-01-18
| | | | | | | | | | | | | | | | | Use the timers API in the gk20a code instead of Linux specific API calls. This also changes the behavior of several functions to wait for the full timeout for each operation that can timeout. Previously the timeout was shared across each operation. Bug 1799159 Change-Id: I2bbed54630667b2b879b56a63a853266afc1e5d8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1273826 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement SET_RD_COALESCETerje Bergstrom2017-01-05
| | | | | | | | | | | | | Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: skip setting preemption modes if already setDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | In gr_gp10b_set_preemption_mode(), skip setting anything if both graphics and compute preemption modes are already set Bug 200263471 Change-Id: I2788464750835da8f6396c6c1ca8356a63758c80 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1275465 GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: use common API to write TPC fusesDeepak Nibade2016-12-27
| | | | | | | | | | | | | Use common fuse write API tegra_fuse_control_write which should work on all kernel versions Bug 200262155 Change-Id: I29e8514e9660549ecf94711287ec4bbf4c897a86 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1270169 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: allow upgrading preemption modesDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | We currently do not allow resetting preemption modes once set Relax this check to allow upgrading preemption modes. Downgrading of preemption modes is still not allowed Bug 200263471 Change-Id: Ie2dae910028929090899a661f4b8b9dd4d6d7ee7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1269472 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: remove debugger check for cilp completion eventDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | We can trigger CILP only if SM debug mode is on. So in fecs interrupt handler, we could have graphics context running for which SM debug mode is disabled. And in that case we skip posting of cilp completion events to UMD. But since CILP event was anyways triggered, we need to post events to UMD irrespective of SM debug mode is enabled at that point or not Hence remove check gk20a_gr_sm_debugger_attached() for posting events to UMD Bug 200243092 Change-Id: I54ad205be11ec6d5034d524bfbb28f8a1fa72993 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1263591 (cherry picked from commit e6259e2d0d5a4bb5929e70e03e154f8b82ae3600) Reviewed-on: http://git-master/r/1264780 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: gp10b: define fuse macro depend on kernel versionShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | | | - Define fuse macros depending on kernel version as fuse offset got changed in K4.4 and for K4.4 fuse defines are defined in common header file (tegra-fuse.h) - Use fuse control read/write APIs when reading control registers for K4.4 Bug 200243956 Change-Id: I34dabd1a307d10010cb89ac6a5f1e3f5b177c0fc Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1245825 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: change the usage of tegra_fuse_readlShardar Shariff Md2016-12-27
| | | | | | | | | | | | | | | tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: send only one event to the debuggerCory Perry2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Event notifications on TSGs should only be sent to the channel that caused the event to happen in the first place, not evey channel in the tsg. Any more and the debugger will not be able to tell what channel actually got the event. Worse yet, if all the channels in a tsg are bound to the same debug session (as is the case with cuda-gdb), then multiple nvgpu events for the same gpu event will be triggered, causing events to be buffered and the client to get out of sync. One gpu exception, one nvgpu event per tsg. Bug 1793988 Change-Id: Iee36c774f193554ffb9ab7c1650ee0610e476a99 Signed-off-by: Cory Perry <cperry@nvidia.com> Reviewed-on: http://git-master/r/1194206 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: post bpt events after processingDeepak Nibade2016-12-27
| | | | | | | | | | | | | | Receive hww_global_esr in gr_gp10b_handle_sm_exception() and pass it to gr_gk20a_handle_sm_exception() Bug 200209410 Change-Id: I467355aa57dd3cf03c4ea2134fbc8691f8e76369 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1194986 GVS: Gerrit_Virtual_Submit Reviewed-by: Cory Perry <cperry@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add preemption mode support for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | | Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x family gr class (PASCAL_B and PASCAL_COMPUTE_B). Bug 200221149 Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1193209 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gp10b: add tpc disable fuse overrideRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | When gp10b added fuse override callback, tpc disable fuse override was missed, which was added in gm20b file. Bug 200220632 Change-Id: I49101a6691f86ccbca390c83f3bd4314eb1a9e36 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1185066 (cherry picked from commit 46f8b7c66d745e80e8c5fc80c19f759ffadf3308) Reviewed-on: http://git-master/r/1189783 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
* gpu: nvgpu: use vidmem by default in gmmu_alloc variantsKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | For devices that have vidmem available, use the vidmem allocator in gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem. Because all of the buffers haven't been tested to work in vidmem yet, rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at the end to declare explicitly that vidmem is used. Enabling vidmem for each now is a matter of removing "_sys" from the function call. Jira DNVGPU-18 Change-Id: I4a67eae403f1d9d271118c35e3775b1129170676 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1176806 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: support in-kernel vidmem mappingsKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that buffers represented as a mem_desc and present in vidmem can be mapped to gpu. JIRA DNVGPU-18 JIRA DNVGPU-76 Change-Id: Icd675e83e3c28836f0ed8880425748697713bb0a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1169296 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: set graphics preemption stateThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | Set NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT from the default of ~20us to ~100us. Also set NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI o avoid going into GFXP all the time. Bug 1593548 Jira VFND-1894 Change-Id: I6310c3605f7b83178c38de88788d87e36ee428b4 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1162629 (cherry picked from commit 873ddc7288063b1773d31a5bda30d980122d6645) Reviewed-on: http://git-master/r/1166988 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove hard coded runlist_id mappingLakshmanan M2016-12-27
| | | | | | | | | | | | | | | From this patch onwards, runlist_id is a member of struct channel_gk20a. So removed hard coded runlist_id mapping logic. JIRA DNVGPU-25 Change-Id: Ib87d96a518a490d4167071708a76100a4d4c02dd Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1161776 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: clear TEX ECC interruptAdeel Raza2016-12-27
| | | | | | | | | | | | Fix bug in clearing the TEX ECC interrupt. Bug 200206379 Change-Id: I758b55d20919173de527aeb98143851edcde4eeb Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1158806 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: map patch ctx in set_preemption_modeKonsta Holtta2016-12-27
| | | | | | | | | | | | The per-write map/unmap feature from gr_gk20a_ctx_patch_write_begin() is dropped, so call begin/end explicitly from gr_gp10b_set_preemption_mode for the commit_global_cb_manager call. Change-Id: I7bf952fffb54d4f18706e77dea015ffe4b68bcfe Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157835 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix patch write error check in update_ctxsw_preemption_modeKonsta Holtta2016-12-27
| | | | | | | | | | | | Don't attempt to access memory if the patch context can't be mapped, but print an error message instead. Change-Id: I374dc94d13674e0bd9d081b790f7c0dac834e868 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157828 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct APIs for disable and preemptDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | In gr_gp10b_set_preemption_mode() and in gp10b_fifo_resetup_ramfc(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above function which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: I2369e79b2af3b8a91699044106293865d5f8f260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157192 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix timeout error in suspend_contextsCory Perry2016-12-27
| | | | | | | | | | | | | | | * Moving jiffy counter after preemption work to more accurately and fairly give time for preemption to complete. * Add debug information to coordinate waiting. * Check if cilp is still pending before returning the timedout error. Bug 1700310 Change-Id: Ic16bb3b11f2cd5aea9a5a85b5e0d9927732a065c Signed-off-by: Cory Perry <cperry@nvidia.com> Reviewed-on: http://git-master/r/1151907 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: SM LRF ECC overcount WARAdeel Raza2016-12-27
| | | | | | | | | | | | | | SM LRF ECC HW overcounts errors in certain situations. Implement SW WAR to correct error counts. Bug 1752609 Bug 1761594 Change-Id: I79047d21e2e44e0fca3ece1da80f02faa4cd6c54 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1150773 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix SM number when more than 4 TPCsTerje Bergstrom2016-12-27
| | | | | | | | | | | Use multiplication instead of division to come up with an SM id. Change-Id: Ib185970ee99cc8c010d02ba846229e0959a5fef3 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150599 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gp10b: Fix CWD floorsweep programmingTerje Bergstrom2016-12-27
| | | | | | | | | | | | Program CWD TPC and SM registers correctly. The old code did not work when there are more than 4 TPCs. Change-Id: I18a14a0f76d97b0962607ec0bbd71aafcd768bca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1143075 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmemKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. JIRA DNVGPU-23 Change-Id: I21d4a54827b0e2741012dfde7952c0555a583435 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1121914 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: add code to handle DT fuse overridesAdeel Raza2016-12-27
| | | | | | | | | | | | | | Add code for handling GP10B fuse overrides specified in the device tree. Also add specific handling for the ECC fuse override. Bug 1699676 Change-Id: Ifa07983054cd143f7f1745a6a6de36f4d4e08126 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/1140893 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: API to return preemption modesDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Add API gr_gp10b_get_preemption_mode_flags() to return supported and default graphics/compute preemption modes on gp10b Bug 1646259 Change-Id: I291a82a911e021b605b6d1ccae9cef663cc7a01a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1133596 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: API to set preemption modeDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Separate out new API gr_gp10b_set_ctxsw_preemption_mode() which will check requested preemption modes and take appropriate action for each preemption mode This API will also do some sanity checking for valid preemption modes and combinations Define API set_preemption_mode() for gp10b which will set the preemption modes passed as argument and then use gr_gp10b_set_ctxsw_preemption_mode() and update_ctxsw_preemption_mode() to update preemption mode Legacy path from gr_gp10b_alloc_gr_ctx() will convert flags NVGPU_ALLOC_OBJ_FLAGS_* into appropriate preemption modes and then call gr_gp10b_set_ctxsw_preemption_mode() New API set_preemption_mode() will use new flags NVGPU_GRAPHICS/COMPUTE_PREEMPTION_MODE_* and set and update ctxsw preemption mode In gr_gp10b_update_ctxsw_preemption_mode(), update graphics context to set CTA premption mode if mode NVGPU_COMPUTE_PREEMPTION_MODE_CTA is set Also, define preemption modes in nvgpu-t18x.h and use them everywhere Remove old definitions of modes from gr_gp10b.h Bug 1646259 Change-Id: Ib4dc1fb9933b15d32f0122a9e52665b69402df18 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1131806 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: suspend context support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | Add API gr_gp10b_suspend_contexts() to support context suspend on gp10b sequence to suspend: - disable ctxsw - loop through list of channels - if channel is ctx resident, suspend all SMs - if CILP channel, set CILP preempt pending = true - resume all SMs - otherwise, disable channel/TSG - enable ctxsw - if CILP preempt is pending, wait for it to complete Bug 200156699 Change-Id: Id9609077c283f99f420ad21c636b29f74b8eff6b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1120334 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add litter values HALTerje Bergstrom2016-12-27
| | | | | | | | | | | Move per-chip constants to be returned by a chip specific function. Implement get_litter_value() for each chip. Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1121384 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: post CILP_PREEMPTION_STARTED/COMPLETE eventsDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Remove posting of events using old channel event API i.e. gk20a_channel_post_event() Also, update gk20a_channel_semaphore_wakeup() to post events when called from ce2_nonblockpipe_isr() Bug 200089620 Change-Id: I677cdab11183a649663ff9272a527c63b9994430 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1112275 (cherry picked from commit 4840efda393cd5928f1a8463db8b52cc586860bc) Reviewed-on: http://git-master/r/1120289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvpgu: setup fecs_trace hal operationsThomas Fleury2016-12-27
| | | | | | | | | | bug 1648908 Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ECC overrideSupriya2016-12-27
| | | | | | | | | | | | | | | | -sysfs functions to call into LS PMU and modify ECC overide register Bug 1699676 Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/921252 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC stats sysfs nodesAdeel Raza2016-12-27
| | | | | | | | | | | Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pass channel pointer to handle sm exceptionDeepak Nibade2016-12-27
| | | | | | | | | | | | | Pass faulting channel pointer to gr_gk20a_handle_sm_exception() instead of NULL Bug 200156699 Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1011289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | fix below sparse warning : drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol 'gr_gp10b_pre_process_sm_exception' was not declared. Should it be static? Bug 200088648 Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1009938 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: post events on all channels of TSGDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | While posting CILP preemption complete event to user space, raise the event to all channels of TSG (if channel is part of TSG) This is a WAR until we have proper sync mechanism with user space to raise CILP events Bug 200156699 Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1001696 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add CILP support for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: mask hww_warp_esr for gp10bDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add API gp10b_mask_hww_warp_esr() to mask hww_warp_esr appropriately on gp10b Bug 200156699 Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/927129 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: add ECC supportAdeel Raza2016-12-27
| | | | | | | | | | | | | Add ECC exception handling support for SM, TEX, and LTC. Bug 1635727 Bug 1637486 Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: http://git-master/r/935362 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r()David Li2016-12-27
| | | | | | | | | | | | | gr_*__set_alpha_circular_buffer_size() left max_batches field of gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta transitions and poor performance when tessellation or geometry shaders are used Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/840079 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix set_circular_buffer_sizeDavid Li2016-12-27
| | | | | | | | | | | | | | | It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r causing a GPU MMU fault when used. Bug 200141640 Bug 200141981 Bug 200141640 Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697 Signed-off-by: David Li <davli@nvidia.com> Reviewed-on: http://git-master/r/807694 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Add tile caching registersTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Add tile caching registers to access map. Bug 1692373 Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/812352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: gp10b: Install gp10b access mapTerje Bergstrom2016-12-27
| | | | | | | | | | | Bug 1692373 Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/812351 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
* gpu: nvgpu: ZBC update without idleTerje Bergstrom2016-12-27
| | | | | | | | | | Do ZBC updates without forcing engine idle first. Bug 1698013 Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/829146
* gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheableAingara Paramakuru2016-12-27
| | | | | | | | | | | | | | | Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 13:30:48 -0400