| Commit message (Collapse) | Author | Age |
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Add code for handling GP10B fuse overrides specified in the device tree.
Also add specific handling for the ECC fuse override.
Bug 1699676
Change-Id: Ifa07983054cd143f7f1745a6a6de36f4d4e08126
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1140893
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add API gr_gp10b_get_preemption_mode_flags() to return
supported and default graphics/compute preemption modes
on gp10b
Bug 1646259
Change-Id: I291a82a911e021b605b6d1ccae9cef663cc7a01a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1133596
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Separate out new API gr_gp10b_set_ctxsw_preemption_mode()
which will check requested preemption modes and take appropriate
action for each preemption mode
This API will also do some sanity checking for valid
preemption modes and combinations
Define API set_preemption_mode() for gp10b which will set the
preemption modes passed as argument and then use
gr_gp10b_set_ctxsw_preemption_mode() and
update_ctxsw_preemption_mode() to update preemption mode
Legacy path from gr_gp10b_alloc_gr_ctx() will convert
flags NVGPU_ALLOC_OBJ_FLAGS_* into appropriate preemption modes
and then call gr_gp10b_set_ctxsw_preemption_mode()
New API set_preemption_mode() will use new flags
NVGPU_GRAPHICS/COMPUTE_PREEMPTION_MODE_* and set and update
ctxsw preemption mode
In gr_gp10b_update_ctxsw_preemption_mode(), update graphics
context to set CTA premption mode if mode
NVGPU_COMPUTE_PREEMPTION_MODE_CTA is set
Also, define preemption modes in nvgpu-t18x.h
and use them everywhere
Remove old definitions of modes from gr_gp10b.h
Bug 1646259
Change-Id: Ib4dc1fb9933b15d32f0122a9e52665b69402df18
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1131806
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add API gr_gp10b_suspend_contexts() to support context
suspend on gp10b
sequence to suspend:
- disable ctxsw
- loop through list of channels
- if channel is ctx resident, suspend all SMs
- if CILP channel, set CILP preempt pending = true
- resume all SMs
- otherwise, disable channel/TSG
- enable ctxsw
- if CILP preempt is pending, wait for it to complete
Bug 200156699
Change-Id: Id9609077c283f99f420ad21c636b29f74b8eff6b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1120334
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move per-chip constants to be returned by a chip specific function.
Implement get_litter_value() for each chip.
Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1121384
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Remove posting of events using old channel event API i.e.
gk20a_channel_post_event()
Also, update gk20a_channel_semaphore_wakeup() to post
events when called from ce2_nonblockpipe_isr()
Bug 200089620
Change-Id: I677cdab11183a649663ff9272a527c63b9994430
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1112275
(cherry picked from commit 4840efda393cd5928f1a8463db8b52cc586860bc)
Reviewed-on: http://git-master/r/1120289
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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bug 1648908
Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1022730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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-sysfs functions to call into LS PMU and modify
ECC overide register
Bug 1699676
Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/921252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add sysfs nodes for querying ECC single/double bit error counts.
Bug 1699676
Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Pass faulting channel pointer to gr_gk20a_handle_sm_exception()
instead of NULL
Bug 200156699
Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1011289
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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fix below sparse warning :
drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol
'gr_gp10b_pre_process_sm_exception' was not declared. Should it be
static?
Bug 200088648
Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1009938
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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While posting CILP preemption complete event to
user space, raise the event to all channels of TSG
(if channel is part of TSG)
This is a WAR until we have proper sync mechanism
with user space to raise CILP events
Bug 200156699
Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1001696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add CILP support for gp10b by defining below function
pointers (with detailed explanation)
pre_process_sm_exception()
- for CILP enabled channels, get the mask of errors
- if we need to broadcast the stop_trigger, suspend all SMs
- otherwise suspend only current SM
- clear hww_global_esr values in h/w
- gr_gp10b_set_cilp_preempt_pending()
- get ctx_id
- using sideband method, program FECS to generate
interrupt on next ctxsw
- disable and preempt the channel/TSG
- set cilp_preempt_pending = true
- clear single step mode
- resume current SM
handle_fecs_error()
- we get ctxsw_intr1 upon next ctxsw
- clear this interrupt
- get handle of channel on which we first
triggered SM exception
- gr_gp10b_clear_cilp_preempt_pending()
- set cilp_preempt_pending = false
- send events to channel and debug session fd
Bug 200156699
Change-Id: Ia765db47e68fb968fada6409609af505c079df53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/925897
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add API gp10b_mask_hww_warp_esr() to mask
hww_warp_esr appropriately on gp10b
Bug 200156699
Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/927129
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add ECC exception handling support for SM, TEX, and LTC.
Bug 1635727
Bug 1637486
Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gr_*__set_alpha_circular_buffer_size() left max_batches field of
gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta
transitions and poor performance when tessellation or geometry
shaders are used
Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/840079
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r
causing a GPU MMU fault when used.
Bug 200141640
Bug 200141981
Bug 200141640
Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: http://git-master/r/807694
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add tile caching registers to access map.
Bug 1692373
Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Bug 1692373
Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812351
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Do ZBC updates without forcing engine idle first.
Bug 1698013
Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/829146
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Some of the allocated buffers are used during normal graphics
processing. Mark them as GPU cacheable to improve performance.
Bug 1695718
Change-Id: I71d5d1538516e966526abe5e38a557776321597f
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/827087
(cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed)
Reviewed-on: http://git-master/r/828493
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value
written in gk20a_init_gr_setup_hw() instead of hard coding here.
Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/813959
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We used to allocate 1.5x buffer size. This leads to memory waste, as
we do not set the CB size via SW methods anymore.
Bug 1686189
Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801865
(cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2)
Reviewed-on: http://git-master/r/815683
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Handle beta CB sizing differences for GfxP versus WFI channels.
Bug 1686189
Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801533
(cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4)
Reviewed-on: http://git-master/r/815682
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Spill buffer size is in chunks of 256B. Multiply the size by
granularity to get the size in bytes.
Bug 1686189
Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801344
(cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0)
Reviewed-on: http://git-master/r/815680
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If pagepool size equals max we should use zero. Add the comparison
to do that.
Bug 1686189
Change-Id: I15bd43663550b1089a726c0256b89f849c193e21
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801526
(cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e)
Reviewed-on: http://git-master/r/815681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Bug 200137963
Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797151
(cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f)
Reviewed-on: http://git-master/r/808241
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement method for setting the coalesce buffer size at runtime.
Bug 1681992
Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/802366
(cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611)
Reviewed-on: http://git-master/r/808239
GVS: Gerrit_Virtual_Submit
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Enabling cyclestats and cyclestats snapshot support for gp10b (t186) devices.
Bug 1674079
Change-Id: I2e14801de3c61d180630bb9dcd2c607749814893
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/792953
Reviewed-on: http://git-master/r/806190
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We program the default steady state beta CB size. The default is
for deep binning, but we've disabled deep binning. As result steady
state CB size was left too high.
Bug 1683535
Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/795306
Reviewed-on: http://git-master/r/806189
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Program correct CB size for GfxP channels. We were accidentally
using the context image size.
Change-Id: I273215256e41e89b7d76f3294a73641804beeb79
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/792713
Reviewed-on: http://git-master/r/806188
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Add debugfs switch to force cilp and gfx preemption
Add debugfs switch to dump context switch stats on channel
destruction.
bug 1525327
bug 1581799
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66
Reviewed-on: http://git-master/r/794976
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677231
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Disable deep binning by default.
Change-Id: I75da95984ac314015c6927e099a3eaa37fcc26fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790403
Reviewed-on: http://git-master/r/806186
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Bug 1678603
Change-Id: Ib8fb09dace864567b1ce574c216a584831723684
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790402
Reviewed-on: http://git-master/r/806185
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Bug 1642669
Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755150
Reviewed-by: Automatic_Commit_Validation_User
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Set address check mode for SM.
Bug 1625763
Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139
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Alpha and beta sizes need to be clipped to a maximum value. For
alpha CB we were using beta size in clipping, and for both we were
not using number of TPCs to determine the max value.
Change-Id: I0c925464ba4c9f575e6e59dd5ba7759aa1cb6381
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752667
Reviewed-by: Automatic_Commit_Validation_User
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Some fields have different widths, so duplicate the code to program
global bundle CB.
Change-Id: Ib6af5abf3e90dfa1bcda2fbc6b97ad1031e6ab16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752635
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Program CB base to new gp10b registers.
Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752634
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When allocating betacb for a GfxP channel, add both alpha and beta
cb sizes together.
Change-Id: I8cef62f6272bfb3b5e9a3835a51590e5eb91dc92
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752633
Reviewed-by: Automatic_Commit_Validation_User
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Expose CILP and GFXP flags to user space ioctl
NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX.
Bug 200111328
Change-Id: I10931db2babd3222e308fd491824d95204355ff3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/748932
GVS: Gerrit_Virtual_Submit
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ZBC is safe to update and GPU is safe to rail gate when units are
in preempted or empty state. Idle may never be reached in case of
graphics preemption, so relax the ZBC update wait condition.
Bug 1640378
Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/745655
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Calculate GFXP attrib cb buffer size from the global buffer size.
Bug 1628352
Change-Id: If4edfbf5700334b791dbf8e5cf38fd0208ee7fa1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/735717
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If betacb size has been given via debugfs, use that instead of the
calculated number.
Bug 1628352
Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/733332
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Add a missing bitmask for clearing existing bits before setting a new
value, and shift the value the correct amount. Also format register
needs to be rounded down.
Bug 200087330
Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/726265
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Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Program steady state CB size to be the HW default.
Bug 1626065
Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/725106
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Move the fifo engine activity disabling and wait-for-idle from the
lowest-level functions higher, into the ioctl path of zbc operations, so
that the sw initialization path wouldn't call them. During the init
path, the disable isn't necessary, and the code path could result in a
deadlock in the fifo runlist mutex.
Change-Id: I56e73204e288331165358fc9856390f1eb724488
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/715196
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Offset for preemption pointer was calculated incorrectly.
Bug 1617214
Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/716528
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Add below exception registers to GR dump :
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN
Bug 200078514
Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/712481
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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