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path: root/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
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* gpu: nvgpu: gp10b: Wait for preempted or emptyTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | ZBC is safe to update and GPU is safe to rail gate when units are in preempted or empty state. Idle may never be reached in case of graphics preemption, so relax the ZBC update wait condition. Bug 1640378 Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/745655 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gp10b: Dynamic GfxP buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | Calculate GFXP attrib cb buffer size from the global buffer size. Bug 1628352 Change-Id: If4edfbf5700334b791dbf8e5cf38fd0208ee7fa1 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/735717
* gpu: nvgpu: gp10b: Use betacb size from debugfsTerje Bergstrom2016-12-27
| | | | | | | | | | | If betacb size has been given via debugfs, use that instead of the calculated number. Bug 1628352 Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/733332
* gpu: nvgpu: set zbc format field properlyKonsta Holtta2016-12-27
| | | | | | | | | | | | | Add a missing bitmask for clearing existing bits before setting a new value, and shift the value the correct amount. Also format register needs to be rounded down. Bug 200087330 Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/726265
* gpu: nvgpu: gp10b: fix sparse warnings of static symbolDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Fix sparse warnings of below type by making necessary symbols static: warning: symbol '<symbol>' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: gp10b: Correct steady state CB sizeTerje Bergstrom2016-12-27
| | | | | | | | | | Program steady state CB size to be the HW default. Bug 1626065 Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725106
* gpu: nvgpu: zbc: disable activity only from ioctlKonsta Holtta2016-12-27
| | | | | | | | | | | | | | Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: I56e73204e288331165358fc9856390f1eb724488 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/715196 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Fix offset for preemption ptrTerje Bergstrom2016-12-27
| | | | | | | | | | Offset for preemption pointer was calculated incorrectly. Bug 1617214 Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/716528
* gpu: nvgpu: add exception registers to dumpDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/712481 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointerKirill Artamonov2016-12-27
| | | | | | | | | | | | | Fixed incorrectly encoded pointer and size. bug 1525327 bug 1581799 Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com> Reviewed-on: http://git-master/r/713209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Enable warnings as errorsTerje Bergstrom2016-12-27
| | | | | | Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/709867
* gpu: nvgpu: gp10b: dump GR status registersDeepak Nibade2016-12-27
| | | | | | | | | | | | | Add function pointer gr_gp10b_dump_gr_status_regs() which will enable dumping GR status registers for gp10b Bug 200062436 Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/678832 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: use tight loop for fecs methodVijayakumar2016-12-27
| | | | | | | | | | | bug 200078367 Change-Id: I9a68e988fa7921276e334c75afa5ee4b15aab464 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/707313 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gp10b: Enable CILP mode for computeTerje Bergstrom2016-12-27
| | | | | | | | | | | Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement gp10b context creationTerje Bergstrom2016-12-27
| | | | | | | | | | | Implement context creation for gp10b. GfxP contexts need per channel buffers. Bug 1517461 Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/660236
* gpu: nvgpu: gp10b: Change order of alpha & betaTerje Bergstrom2016-12-27
| | | | | | | | | Change order of alpha & attribute buffers in CB. The new order follows RM. Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657907
* gpu: nvgpu: gp10b: Program CB sizesTerje Bergstrom2016-12-27
| | | | | | | | | | | Program CB sizes. Bug 1567274 Change-Id: Idc88f69b70e85bf950af852a9ca80a328d95883f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654097 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Implement SW methodsTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/654098
* gpu: nvgpu: gp10b: Calc global context buffer sizeTerje Bergstrom2016-12-27
| | | | | | | | | | In gp10b we need to limit global context buffer size, and it needs to be 128b aligned. Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/657911 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10b: Define pagepool sizeTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1567274 Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606932 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Write ZBC registers to DSSTerje Bergstrom2016-12-27
| | | | | | | | Bug 1567274 Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601108
* gpu: nvgpu: gp10b specific CB callbacksTerje Bergstrom2016-12-27
| | | | | | | | | Bug 1570662 Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/592101 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: t18x, gp10b frameworkKenneth Adams2016-12-27
This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams <kadams@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit
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