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path: root/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
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* gpu: nvgpu: rename hw_chid to chidRichard Zhao2017-06-30
| | | | | | | | | | | | | hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: I1c7924da1757330ace715a7c52ac61ec9dc7065c Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master/r/1509530 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: split vidmem_is_vidmemKonsta Holtta2017-06-06
| | | | | | | | | | | | | | | | | | | | | As the vidmem_is_vidmem flag has got two separate meanings in one bit, split it in two bits into the enabled() API: Add NVGPU_MM_HONORS_APERTURE bit, which is the same as vidmem_is_vidmem with its original meaning, and use it to test which aperture bits to write to hardware. Add NVGPU_MM_UNIFIED_MEMORY bit, which has the opposite meaning: that the GPU shares the SoC memory. When this flag is false, the GPU has its own local video memory. Jira NVGPU-86 Change-Id: I2d0bed3b1ede5a712be99323d3035b154bb23c3a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1496080 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops get_mmu_fault_infoSeema Khowala2017-05-30
| | | | | | | | | | | | | | | | | | | | This is needed to take care of gp10b h/w header changes. gp10b changes as compared to legacy gpu chips -fault_info_fault_type field width is changed -fault_info_write field is removed -fault_info_access_type field is added -fault_info_engine_subid is removed -fault_info_client_type is added -fault_info_client field width has changed JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Iebf28cc6c851830524049b67a71cd72fb4a28948 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1487319 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add wrapper nvgpu/log2.hDeepak Nibade2017-04-20
| | | | | | | | | | | | | Add wrapper header file nvgpu/log2.h. It #includes <linux/log2.h> in Linux. JIRA NVGPU-13 Change-Id: Ie434e62f7ef2dce7692b1c2c12b4ad6453f1534a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1464719 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Use new delay APIsTerje Bergstrom2017-04-13
| | | | | | | | | | | | | | | Use platform agnostic delay functions instead of Linux kernel APIs. This allows removing dependency to Linux header linux/delay.h. At the same time remove #include lines for other unused Linux headers. JIRA NVGPU-16 Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1460114 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Add wrapper nvgpu/bug.hTerje Bergstrom2017-04-13
| | | | | | | | | | | | | Add wrapper header file nvgpu/bug.h. It #includes <linux/bug.h> in Linux. JIRA NVGPU-13 Change-Id: I7bf02ba554333f7cbd79d72bd1cb423c81ebcb49 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1461545 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp10b: Use new error macrosTerje Bergstrom2017-04-10
| | | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8dc0ddf3b6ea38af6300c27558b60786c163da6d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457344 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Move DMA API to dma.hAlex Waterman2017-04-06
| | | | | | | | | | | | | | | Make an nvgpu DMA API include file so that the intricacies of the Linux DMA API can be hidden from the calling code. Also document the nvgpu DMA API. JIRA NVGPU-12 Change-Id: I7578e4c726ad46344b7921179d95861858e9a27e Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323326 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename mem_desc to nvgpu_memAlex Waterman2017-04-06
| | | | | | | | | | | | | | | | | Renaming was done with the following command: $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' Also rename mem_desc.[ch] to nvgpu_mem.[ch]. JIRA NVGPU-12 Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1325547 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rename gk20a_mem_* functionsAlex Waterman2017-04-06
| | | | | | | | | | | | Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323325 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add wrapper for linux/types.hTerje Bergstrom2017-04-03
| | | | | | | | | | | | | | | | Add wrapper header nvgpu/types.h. It checks if build is for Linux kernel and pulls in linux/types.h. Delete also all #includes for linux/types.h which are not strictly necessary, and change the remaining ones to use the new wrapper. JIRA NVGPU-13 Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1453371 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move programming of host registers to fifoTerje Bergstrom2017-03-28
| | | | | | | | | | | | | | | | | | | Move code that touches host registers and instance block to fifo HAL. This involves adding HAL ops for the fifo HAL functions that get called from outside fifo. This clears responsibility of channel by leaving it only managing channels in software and push buffers. channel had member ramfc defined, but it was not used, to remove it. pbdma_acquire_val consisted both of channel logic and hardware programming. The channel logic was moved to the caller and only hardware programming was moved. Change-Id: Id005787f6cc91276b767e8e86325caf966913de9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1322423 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add init_pbdma_intr_desc fifo opsSeema Khowala2017-03-23
| | | | | | | | | | | | | | | | | | | | | | Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks for each GPU version separately pbdma_intr_0 field differences for each GPU version:- -gk20a : bit 28 does not exists in hw -gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw -gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28, (syncpoint_illegal) added in hw but is not being handled. -gk20a/gm20b/gp10b bit 24 eng_reset and bit 25 semaphore always existed in hw but never handled JIRA GPUT19X-47 Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1325402 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: add fifo ops for *data_fault_id_enum_vSeema Khowala2017-03-02
| | | | | | | | | | | | | generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: I877e88a5b1b1f3f41bc72b895536f4a01b4fbd4e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1313384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move gp10b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp10b HW headers to a new directory specially for them: include/nvgpu/hw/gp10b And change the code to include like so: #include <nvgpu/hw/gp10b/hw_fb_gp10b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280326 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: make commit_userd globalseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | Make channel_gp10b_commit_userd global, so other gpus can re-use that function. JIRA GV11B-11 Change-Id: Ibe03063befc2da6c67822121f880a141cad46e84 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1237738 GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Do not print error on unknown engineTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | Unknown engine is expected, as we do not support all dGPU engines. Remove the error spew. JIRA DNVGPU-26 Change-Id: I3d43253b8cab4e51b426536e4899a62156d0da16 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1206465 (cherry picked from commit a3fa13f6be4ff60e90558326474af3d1b315aa43) Reviewed-on: http://git-master/r/1208408 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add interface for privileged channel allocationLakshmanan M2016-12-27
| | | | | | | | | | | | | Added interface for privileged channel allocation to execute the privileged method (ex. CE phys mode transfer). JIRA DNVGPU-53 Change-Id: I1606f8c9d10f29d5a10738b5110ce9f6a2bb428d Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1169320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use correct APIs for disable and preemptDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | In gr_gp10b_set_preemption_mode() and in gp10b_fifo_resetup_ramfc(), we call channel specific APIs to disable/preempt/enable channel But we do not consider TSGs in this case Hence use correct (below) APIs in above function which will handle channel or TSG internally : gk20a_disable_channel_tsg() gk20a_fifo_preempt() gk20a_enable_channel_tsg() Bug 200205041 Change-Id: I2369e79b2af3b8a91699044106293865d5f8f260 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1157192 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | Added device_info_data parsing support for pascal GPU series. This is required to identify the (Logical CE) NV_PTOP_DEVICE_INFO_TYPE_ENUM_LCE instance id. (example - CE0, CE1, CE2, CE3, ...) JIRA DNVGPU-26 Change-Id: I35c42cb1d544729e4099db1528c690dd2be025f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151605 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: Implement engine_enum_from_typeTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement a helper function engine_enum_from_type. This allows parsing device_info entries for LCE engine type. Pascal has logical copy engine instead of CE2, so so add definition of that. Change-Id: I71f59c308641d84ac59fd57fc37d9b627bb07a43 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1147747 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: refactor gk20a_mem_{wr,rd} for vidmemKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | To support vidmem, pass g and mem_desc to the buffer memory accessor functions. This allows the functions to select the memory access method based on the buffer aperture instead of using the cpu pointer directly (like until now). The selection and aperture support will be in another patch; this patch only refactors these accessors, but keeps the underlying functionality as-is. JIRA DNVGPU-23 Change-Id: I21d4a54827b0e2741012dfde7952c0555a583435 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1121914 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: gp10b: Use sysmem aperture for SoC memoryTerje Bergstrom2016-12-27
| | | | | | | | | | | | | In Tegra GPU, SoC memory has to be accessed as vidmem. In discrete GPU, it has to be accessed as sysmem. Change-Id: Id26588df17b4921533804f72bc8c0ac3892ae154 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1122591 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: enable semaphore acquire timeout for gp10bRichard Zhao2016-12-27
| | | | | | | | | | | | | | | | | It'll detect dead semaphore acquire. The worst case is when ACQUIRE_SWITCH is disabled, semaphore acquire will poll and consume full gpu timeslicees. The timeout value is set to half of channel WDT. Bug 1636800 Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/928830 Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Lazy sync point updateTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | Update sync point protection field only when we have a valid sync point id, and the new id is different from old id. Bug 1653328 Change-Id: Ie07e26f8abd7c8239ad562603b62fda00164cbc7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/757102 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
* gpu: nvgpu: Disable channel when writing syncpt idTerje Bergstrom2016-12-27
| | | | | | | | | | | | Kick channel off PBDMA before writing new sync point id to allowed sync points. Bug 1648297 Bug 1646477 Change-Id: I7c686d474c403fdd54bc64cff63b7d049feecb4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/750981
* gpu: nvgpu: gp10b: Use correct PBDMA sigTerje Bergstrom2016-12-27
| | | | | | | | Change-Id: Ic71ff2408bd01a1bf5cf1354453a2fe715438cf0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/751555 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu:nvgpu: gp10b: update channel_setup_ramfcSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | Enable re-playable faults based on characteristics flags passed in channel_setup_ramfc. Bug 1645628 Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/743382 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement syncpt protectionTerje Bergstrom2016-12-27
| | | | | | | | | Change-Id: I05b2554588e5e1001cdbb54551cf8a064ea531bd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/711303 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gp10b: Use mem_desc for buffersTerje Bergstrom2016-12-27
| | | | | | Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/712836
* gpu: nvgpu: gp10b: support for replayable faultsSeshendra Gadagottu2016-12-27
| | | | | | | | | | | | | | | Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10b: Set correct PBDMA signatureTerje Bergstrom2016-12-27
GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/672921
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