| Commit message (Collapse) | Author | Age |
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Add support for enabling replayable faults during
channel instance block binding. Also fixed register
programing sequence for setting channel pbdma timeout.
Bug 1587825
Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/681703
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ce interrupts use different register mapping
and format from gk20a and gm20b.
Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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GPFIFO class was set to Maxwell class number. Also implement the
PBDMA signature HAL.
Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672921
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Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709867
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Remove hard coded NETB for gp10b. This enables cycling through
available firmware files.
Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/676557
Reviewed-by: Peng Du <pdu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Temporally used gm20b elpg sequencing values for gp10b elpg.
Bug 1525971
Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/662517
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Bug 1567274
Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/606931
GVS: Gerrit_Virtual_Submit
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GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.
Bug 1567274
Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
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Bug 1567274
Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/602858
Reviewed-by: Automatic_Commit_Validation_User
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Add gp10b platform data to enable sync point support.
Bug 1572701
Change-Id: Iaf03ecb8fb6b8bf4bb824e2a012c80dfe3f4fcae
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592099
Reviewed-by: Automatic_Commit_Validation_User
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Bug 1567274
Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/591628
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.
Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
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