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* gpu: nvgpu: Prune clock gating listTerje Bergstrom2017-01-31
| | | | | | | | | | | | Prune from clock gating list the entries that target units that do not exist on gp106. Change-Id: I192219a24d8e67de7c1fc25276dfcccbe041a05f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Propagate pmu initialization failuresDavid Nieto2017-01-31
| | | | | | | | | | | | | | | | | During testing it was detected that a failure in loading the firmware for the driver would not propagate, allowing some function pointers to be left unitialized. This would cause a kernel-crash later on. Bug 1866370 Change-Id: I66056a1d99229d10635293d4c1685f596f197255 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1295376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable ECC sysfs in GP106David Nieto2017-01-26
| | | | | | | | | | | | | | The current wiring causes an attempt to re-create the stats on dGPU re-bind bug 1816516 Change-Id: Idb9aea08c9f80325f6ce860b2e0e482e42e973f8 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291822 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GPU reset for gp106 XVEAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | Resets the GPU without resetting the XVE/XP interfaces. This allows the GPU to stay attached to the PCI bus but still resets all the rest of the GPU's internal state. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287644 Reviewed-on: http://git-master/r/1287650 (cherry picked from commit c14efaee5d03a053d5bf229425a7594e1c6bfad0) Change-Id: If7aba3cc8109e30bd6b6aa145836e812d50b35c5 Reviewed-on: http://git-master/r/1292699 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL to get current pstateMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | - Added HAL support to get current pstate from clk_arb Note - This function is inherently unsafe to call while arbiter is running arbiter must be blocked before calling this function JIRA DNVGPU-165 Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1286378 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gp106 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alert limit IOCTL for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | Added the thermal alert lmit IOCTL for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I43a3a5df18467e05c32d043f49440d2086438ebe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1249490 (cherry picked from commit b4123e45956bd02994fd284e8bfd6ce015aa0867) Reviewed-on: http://git-master/r/1282082 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: I54ab0dc35a940e70733238fd95669db28389619a Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248968 (cherry picked from commit a20593c89a374d64201e4720552160a65533ecc3) Reviewed-on: http://git-master/r/1282076 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add read and ioctl for eventsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Add support for poll/read/ioctl for events in clock arbiter. Jira DNVGPU-186 Change-Id: Id95264fffae2b83a388ff8f186ebe7d723029b7f Reviewed-on: http://git-master/r/1253659 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 8d652a7313722aab331f82f0841b490ca25cb51d) Reviewed-on: http://git-master/r/1280885 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement SET_RD_COALESCETerje Bergstrom2017-01-05
| | | | | | | | | | | | | Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement permanent disable_aspmAlex Waterman2017-01-04
| | | | | | | | | | | | | | Implement the permanent disable_aspm() function for XVE on gp106. Bug 200256272 Change-Id: I63338415542381d8a43d746d9d4404a74a5f01cd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1263273 (cherry picked from commit 7890419f242a50c6d8ec27c3e8eb331823230ed9) Reviewed-on: http://git-master/r/1280309 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: FECS trace support on gp106Thomas Fleury2017-01-04
| | | | | | | | | | | | | Enable FECS ctxsw tracing for gp106. Ensure that FECS records have been written to memory before accessing the ring. Update read index only once all records have been processed. Jira EVLR-424 Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1258243 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPPG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Added rppg module to init GR/MS-RPPG. mscg is dependent on gr-rppg & without gr-rppg engage mscg does not engage. - Update pg engines HAL to return supported pg engines & its sub features JIRA DNVGPU-71 Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247486 (cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9) Reviewed-on: http://git-master/r/1270762 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: arb: fix rounding in effective clocksDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | Current code cast casting the frequency to 16 bit before division, giving out incorrect data JIRA DNVGPU-164 Change-Id: I4eb1fa73fb9e8963f550d3d853db39b49b990fa4 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251663 (cherry picked from commit c0d91a054f8278af9a2383bb3f837465779132a9) Reviewed-on: http://git-master/r/1274546 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cap minimum gpc clocks to HW limitsDavid Nieto2016-12-27
| | | | | | | | | | | | | | | JIRA: DNVGPU-180 Change-Id: I1928e77cea4ac87bf2ba2b6b7b2f2942dfb97de9 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251493 (cherry picked from commit 7b8a105652a3169d9ec0cb7ce52c3b92e42ca310) Reviewed-on: http://git-master/r/1274545 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: keep sec2 idleMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | sec2 falcon reset after secure boot complete to keep sec2 idle issue: ELPG does not engage if PG engine is dependent on sec2 idleness JIRA DNVGPU-71 Change-Id: If264c610dae857ae9b9f9bc77c59f24f239ce1ce Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247290 (cherry-picked from commit de2337de1211e4167993982e50237fe1115053a1) Reviewed-on: http://git-master/r/1267260 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: update pg engine init/list/features HALMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - Updated gp10b_pg_gr_init() to post init param based on PG engine parameter - Assigned pg engine list/features HAL to respective functions/NULL JIRA DNVGPU-71 Change-Id: I7d059796746694b22800c6ae0327cbc90331e929 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247407 (cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502) Reviewed-on: http://git-master/r/1269321 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: handle vf curve change due to tempVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-129 1)send 150'c as default temperature to PMU so that PMU will start reading temperature from sensor to evaluate VFE equations 2)Send GP106's temp min and max range for GPU sensor so that PMU will read right temperature 3)PMU will send event whenever temperature goes above +ve hysteresis or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation function in the event handler. Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245392 (cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7) Reviewed-on: http://git-master/r/1268062 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: resolve signed/unsigned mismatchDavid Nieto2016-12-27
| | | | | | | | | | | JIRA DNVGPU-143 Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1268107 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: get voltage, current, power and temperatureThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | Add ioctls to retrieve voltage, current, power and temperature. Add flags in GPU characteristics to indicate if feature is supported. Jira DNVGPU-166 Change-Id: Ifaafe2efdb6b09d7b28215b641814f28e894151e Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1241861 Tested-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267122
* gpu: nvgpu: gpu: read effective frequence from counterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | (1) modified counters debug code to export to the driver (2) modified arbiter to read from those functions (3) modified counter for higher accuracy on MHz range JIRA DNVGPU-164 Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239467 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268008
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Use bootstrap base for WPR addressTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | Use the bootstrap base address for calculating the address of WPR. The bootstrap base is dynamic and depends on amount of memory, so we should not hard code any address. Bug 200244445 Change-Id: Ia700d24c8d572a25946f7b1847faec72c40c6796 Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1242252 Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1267125 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clk requests completion and event fdsThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | Install one completion fd per SET request. Notifications on dedicated event fd. Changed frequencies unit to Hz from MHz. Remove sequence numbers from dummy arbiter. Added effective clock type (query frequency from counters). Jira DNVGPU-125 Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1230239 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560) Reviewed-on: http://git-master/r/1243106
* gpu: nvgpu: clk arbiter skeletonThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | | Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: correct adc slope ofset sign bitVijayakumar2016-12-27
| | | | | | | | | | | | | | bug 1838549 Change-Id: I40457aebd49a02d0dd54d6dc9c965f89613ee21f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1251371 (cherry picked from commit 2c80f36830baf48bab043d7f1ebbcbe7759789c4) Reviewed-on: http://git-master/r/1251452 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add FBPA base addressesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add FBPA base addresses Bug 200249125 Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1247802 (cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a) Reviewed-on: http://git-master/r/1252163 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Program RX bias currentTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Hard code RX bias current to 0x2. Bug 1833830 Change-Id: I1107bad52de7b38d311bc5795739777a4bb4239a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1253656 (cherry picked from commit 7e853b0c62043cc53847e3535e05886d574dc779) Reviewed-on: http://git-master/r/1255724 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10x: updated API for get_litter_valueseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | get_litter_value API is updated to use int instead of enum type. JIRA GV11B-21 Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1252212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix signed comparison bugsTerje Bergstrom2016-12-27
| | | | | | | | | | | | Fix small problems related to signed versus unsigned comparisons throughout the driver. Bump up the warning level to prevent such problems from occuring in future. Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106: Add regops whitelistsPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add regops whitelists for gp106. The whitelist is generated, and is the same for context switched and global registers. Bug 200239422 Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1243253 (cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db) Reviewed-on: http://git-master/r/1247645 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Free pmu_sig if init PMU failsTerje Bergstrom2016-12-27
| | | | | | | | | | | If gk20a_init_pmu() fails, go to the error path that frees pmu_sig. Change-Id: I2f6fcb86570aba54ab45aec14ee6f341e3faebd5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Return correct GPC base addressesTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Due to missing break statements, GPC base and GPC shared base were overwritten by values in following select cases. Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249970 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: gp106: Add PMU HAL is_pmu_supportedTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Add implementation for PMU HAL is_pmu_supported to gp106. JIRA GV11B-21 Change-Id: If4268465ffade7c3c8e7bb853a1d2070c0e2ae4f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1246026 Tested-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Update volt pwm source & raw periodMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - calculate raw period as per pwm source - update pwm source for logic & sram rails. JIRA DNVGPU-123 Change-Id: I50b41d51b6aba760710700522dced7859f815463 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227626 (cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4) Reviewed-on: http://git-master/r/1244663 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: At FB reset wait for scrubberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | We need to wait for scrubber to have finished before we can allow any accesses to memory. Do the wait in place where on iGPU we would do FB reset. Bug 1799537 Bug 1815139 Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235541 (cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc) Reviewed-on: http://git-master/r/1239955 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix sparse warning in LTC codeDavid Nieto2016-12-27
| | | | | | | | | | | | bug 200088648 sparse warning reported that the function was not defined. This was due to a missing include Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1237845 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: parse and execute mclk shadow scriptDavid Nieto2016-12-27
| | | | | | | | | | | | | * Parsing of shadow registers from VBIOS * Partial devinit engine interpreter implementation JIRA DNVGPU-117 Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1214956 Reviewed-on: http://git-master/r/1237293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move ELCG programming to thermTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement gp10b and gp106 ELCG programming. JIRA DNVGPU-74 Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1220431 (cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f) Reviewed-on: http://git-master/r/1239422 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add accessors for invalid ctx_statusDeepak Nibade2016-12-27
| | | | | | | | | | | Bug 1826768 Change-Id: I8be2b9c074868206cb95b3bc84d66ea84683b19a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1237522 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Cory Perry <cperry@nvidia.com>
* gpu: nvgpu: implement PCIe Gen2 frequency swapAlex Waterman2016-12-27
| | | | | | | | | | | | | | | | | | | | Implement the basic code to swap between PCIe bus speeds for the GPU. Other GPUs are not supported yet. Currently the following speeds can be used: Gen1 (2.5 MTPS) Gen2 (5.0 MTPS) gp106 on DPX2 does not support Gen3. JIRA DNVGPU-89 Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499 Reviewed-on: http://git-master/r/1218177 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1227925 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: Add debugfs entry for temperature readingLakshmanan M2016-12-27
| | | | | | | | | | | | | | | Added current temperature reading support for gp10x. JIRA DNVGPU-48 Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1213717 (cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b) Reviewed-on: http://git-master/r/1234092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Suppress error msg from VBIOS overlayTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Suppress error message when nvgpu tries to load VBIOS overlay, but one is not found. This situation is normal. This is done by moving gk20a_request_firmware() to be nvgpu generic function nvgpu_request_firmware(), and adding a NO_WARN flag to it. Introduce also a NO_SOC flag to suppress attempt to load firmware from SoC specific directory in addition to the chip specific directory. Use it for dGPU firmware files. Bug 200236777 Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1223839 (cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d) Reviewed-on: http://git-master/r/1233412 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: MCLK P8/P5 sequences and APIDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | Adds P5/P8 sequences and simple debugfs API to change from P0->P5 JIRA DNVGPU-117 Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1208655 (cherry picked from commit dd410a86263e2407e043743945cf09a77910d745) Reviewed-on: http://git-master/r/1231035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update PMU bootloader paramsMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Bootloader of PMU is changed & bootloader takes params using flcn_bl_dmem_desc_v1 descriptor to boot PMU JIRA DNVGPU-116 Change-Id: I005b615b2323678fa605d190c6b9b629976f0b74 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212818 (cherry picked from commit 89976a03c13cce6bbba25c99270b0da4ca0f2441) Reviewed-on: http://git-master/r/1223842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 17:10:31 -0400