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path: root/drivers/gpu/nvgpu/gp106
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* gpu: nvgpu: Add interface for privileged channel allocationLakshmanan M2016-12-27
| | | | | | | | | | | | | Added interface for privileged channel allocation to execute the privileged method (ex. CE phys mode transfer). JIRA DNVGPU-53 Change-Id: I1606f8c9d10f29d5a10738b5110ce9f6a2bb428d Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1169320 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select FW based on ARCHMahantesh Kumbar2016-12-27
| | | | | | | | | | JIRA DNVGPU-34 Change-Id: Iea1964c7d12536591659188c8e969fc7fb632d12 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1166785 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add new CE class for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | Added new CE class(PASCAL_DMA_COPY_B) for gp106 and gp104. JIRA DNVGPU-25 Change-Id: I3c85e3ffdedf7594d41bf5c2fbebbf44addd1720 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1166709 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: ngpu: gp106: use vidmem allocator for ucode blobKonsta Holtta2016-12-27
| | | | | | | | | | | | | Use the general video memory allocator for reserving wpr space for acr ucode blob instead of crafting a mem_desc manually. Jira DNVGPU-16 Change-Id: I9d34b3b964eb9ab781fcebecd15ba81643c5452d Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1165642 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add fifo conf support for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | Added fifo configuration support for gp104 and gp106. These GPU chips have more number of channel fifo and runlist than gp10b. Added get_num_fifos and eng_runlist_base_size function pointer to find out the actual value from HW headers. JIRA DNVGPU-25 Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1164653 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: WPR updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - setting WPR at 188MB of VIDMEM - setting 256/512MB location at VIDMEM for WPR cause ACR boot failure on GP104/GP106 PROD board but works fine for DEBUG board, - Removed unwanted WPR info dump JIRA DNVGPU-34 Change-Id: I44f9861774fe77dd534d316d91ed9f8dfcb298b4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1164840 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Enable GP10x GPMU secure bootMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | Build support & enable GPMU secure boot for GP10x JIRA DNVGPU-34 Change-Id: Id1316677ed44790aa150e0ada8ff39daf0ef1d0c Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161174 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PMU/SEC2 reset sequence & OPS updateMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | - Enable OPS to support secure boot - PMU/SEC2 reset sequence change for GP104/GP106 JIRA DNVGPU-34 Change-Id: I583a6af1d5354649c3df9d9b4d74141d52d6ca9d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161132 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR boot on SEC2Mahantesh Kumbar2016-12-27
| | | | | | | | | | | | | ACR/SEC2 methods to support ACR boot SEC2 falcon JIRA DNVGPU-34 Change-Id: I917be1d6c61a1c1ae61a918f50228ea00492cd50 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161122 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ACR interface update for GP104/GP106Mahantesh Kumbar2016-12-27
| | | | | | | | | | | JIRA DNVGPU-34 Change-Id: Ieb8e73451a5d73480b8d9e29e78b1a273b17d796 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1161120 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: include matching header in mm_gp106.cKonsta Holtta2016-12-27
| | | | | | | | | | | | | Include mm_gp106.h in mm_gp106.c to bring function declarations visible and to fix a Sparse warning. Bug 200088648 Change-Id: Id76f565021de585bc02a53a01e52084ff70009c2 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1161607 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: detect vidmem configuration from HWKonsta Holtta2016-12-27
| | | | | | | | | | | | | Read video memory size from hardware during initialization for devices that support it. JIRA DNVGPU-14 Change-Id: I84e1bca0eaac8dc204e1fb82628acc6b52c3e5cc Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1157212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add multiple engine and runlist supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | | This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add device_info_data supportLakshmanan M2016-12-27
| | | | | | | | | | | | | | | | | | | Added device_info_data parsing support for pascal GPU series. This is required to identify the (Logical CE) NV_PTOP_DEVICE_INFO_TYPE_ENUM_LCE instance id. (example - CE0, CE1, CE2, CE3, ...) JIRA DNVGPU-26 Change-Id: I35c42cb1d544729e4099db1528c690dd2be025f4 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1151605 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
* gpu: nvgpu: fix sparse warningDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | fix below sparse warning : $TOP/kernel-nvgpu-t18x/drivers/gpu/nvgpu/gp106/pmu_gp106.c:22:5: warning: symbol 'gp106_pmu_reset' was not declared. Should it be static? Bug 200088648 Change-Id: I86120fb6b9733f256c96764a77c6ea4bb636934a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1154452 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Add support for gp104 and gp106Terje Bergstrom2016-12-27
Add support for chips gp104 and gp106. Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120465 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams <kadams@nvidia.com>
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