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* gpu: nvgpu: Rename gk20a_mem_* functionsAlex Waterman2017-04-06
| | | | | | | | | | | | Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323325 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove vmalloc.h and slab.h usageAlex Waterman2017-04-04
| | | | | | | | | | | | | | Remove all usage of vmalloc.h and slab.h outside of the Linux specific kmem API implementation code. Bug 1799159 Bug 1823380 Change-Id: I5b2a91bd1057b272efeaddc24902f6133b35024f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1331703 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move channel IOCTL code to Linux moduleTerje Bergstrom2017-04-04
| | | | | | | | | | | | | Move channel IOCTL specific code to Linux module. This clears some Linux dependencies from channel_gk20a.c. JIRA NVGPU-32 Change-Id: I41817d612b959709365bcabff9c8a15f2bfe4c60 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1330804 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add wrapper for linux/types.hTerje Bergstrom2017-04-03
| | | | | | | | | | | | | | | | Add wrapper header nvgpu/types.h. It checks if build is for Linux kernel and pulls in linux/types.h. Delete also all #includes for linux/types.h which are not strictly necessary, and change the remaining ones to use the new wrapper. JIRA NVGPU-13 Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1453371 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Split out pramin codeAlex Waterman2017-03-31
| | | | | | | | | | | | | Split out the pramin interface code in preparation for splitting out the mem_desc code. JIRA NVGPU-12 Change-Id: I3f03447ea213cc15669b0934fa706e7cb22599b7 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323323 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in mclk codeDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_mclk.c - declare new callback g->ops.pmu.mclk_deinit() to deinitialize mclk mutexes - and define this callback for gp106 - add corresponding nvgpu_mutex_destroy calls in deinitialization Jira NVGPU-13 Change-Id: I1491c084d330ac9756c9520477e6fe494560e651 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321294 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: check return value of mutex_init in clk codeDeepak Nibade2017-03-30
| | | | | | | | | | | | | | | - check return value of nvgpu_mutex_init in clk_gk20a.c/clk_gm20b.c/clk_gp106.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: If6ddc2c924e1ab13274b857f904859033722479a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1321293 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove unnecessary use of dev_name()Terje Bergstrom2017-03-28
| | | | | | | | | | | | | | | Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: Ic6e99e39258cbf3bb7c806962cbbd7de5126688f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1328534 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use new kmem API functions (gp106/*)Alex Waterman2017-03-28
| | | | | | | | | | | | | | | | | | | | | Use the new kmem API functions in gp106/*. Update lsfm_free_ucode_img_res() lsfm_free_nonpmu_ucode_img_res() to take a struct gk20a pointer so that the free can be done with nvgpu_kfree(). Bug 1799159 Bug 1823380 Change-Id: I101f5b87db6cfc7c47d88c8fb158e21947502e3a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1318319 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use nvgpu_timeout for all loopsTerje Bergstrom2017-03-27
| | | | | | | | | | | | | | | | | | | | There were still a few remaining loops where we did not use nvgpu_timeout and required Tegra specific functions for detecting if timeout should be skipped. Replace all of them with nvgpu_timeout and remove including chip-id.h where possible. FE power mode timeout loop also used wrong delay value. It always waited for the whole max timeout instead of looping with smaller increments. If SEC2 ACR boot fails to halt, we should not try to check ACR result from mailbox. Add an early return for that case. JIRA NVGPU-16 Change-Id: I9f0984250d7d01785755338e39822e6631dcaa5a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323227
* gpu: nvgpu: Add bus HALTerje Bergstrom2017-03-23
| | | | | | | | | | | Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: abstract away dma alloc attrsKonsta Holtta2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | Don't use enum dma_attr in the gk20a_gmmu_alloc_attr* functions, but define nvgpu-internal flags for no kernel mapping, force contiguous, and read only modes. Store the flags in the allocated struct mem_desc and only use gk20a_gmmu_free, remove gk20a_gmmu_free_attr. This helps in OS abstraction. Rename the notion of attr to flags. Add implicit NVGPU_DMA_NO_KERNEL_MAPPING to all vidmem buffers allocated via gk20a_gmmu_alloc_vid for consistency. Fix a bug in gk20a_gmmu_alloc_map_attr that dropped the attr parameter accidentally. Bug 1853519 Change-Id: I1ff67dff9fc425457ae445ce4976a780eb4dcc9f Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1321101 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move all FB programming to FB HALTerje Bergstrom2017-03-17
| | | | | | | | | | | | | | | | | | | | | Move all programming of FB to fb_*.c files, and remove the inclusion of FB hardware headers from other files. TLB invalidate function took previously a pointer to VM, but the new API takes only a PDB mem_desc, because FB does not need to know about higher level VM. GPC MMU is programmed from the same function as FB MMU, so added dependency to GR hardware header to FB. GP106 ACR was also triggering a VPR fetch, but that's not applicable to dGPU, so removed that call. Change-Id: I4eb69377ac3745da205907626cf60948b7c5392a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1321516 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement get_rate/set_rate as GPU opTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | | | | | | Move clock APIs from gk20a_platform to gpu_ops. At the same time allow use of internal get_rate/set_rate for querying both GPCCLK and PWRCLK on iGPU. At the same time we can replace calls to clk framework with the new HAL and drop direct dependency to clk framework. gp10b ops were replaced as a whole at HAL initialization. That replaces anything set in platform probe stage, so reduce that to touch only clock gating regs. Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300113 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Rename clk->get_rate to measure_freqTerje Bergstrom2017-03-16
| | | | | | | | | | | | | | get_rate is already used for call-back that queries the last set clock rate. This instance of get_rate actually measures the frequency so renaming it to measure_freq. At the same time modify to use hertz instead of megahertz. We use fractional megahertz already in GPU. Change-Id: I387473d6a6cbf3bb9b9e5a909677a1a725403c32 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1300111 Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: Do not query SEC2 freq from CCFTerje Bergstrom2017-03-14
| | | | | | | | | | | | | | | | | | | dGPU's SEC2 is passed frequency, which is queried with clk_get_rate(). dGPU clocks are not represented in CCF, so the query always returned an error. The value is ignored, so this went unnoticed. Replace the call to clk_get_rate() by just hard coding 0 as the clock rate. Change-Id: I86fec3726d2b6683cdadd86cab1672f3b199378f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1319068 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
* gpu: nvgpu: Remove nvgpu_gpuid_t18x.hAlex Waterman2017-03-02
| | | | | | | | | | | | | | | Remove nvgpu_gpuid_t18x.h since this file is now visible. Migrate the relevant definitions and defines into their expected places and make the code use the real defines. No longer is hiding t18x specific stuff necessary. Bug 1799159 Change-Id: I47fa2392e46fdb7aacc70aeb0cc8c3f5ca0dc22f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1300976 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: pmu: make gp106_pmu_reset() public.Deepak Goyal2017-02-24
| | | | | | | | | | | | | | secure PMU reset i.e. gp106_pmu_reset() is changed to a non-static function, so that it can be re-used outside gp106 scope. Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1303758 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: ACR interface headers reorganizationMahantesh Kumbar2017-02-23
| | | | | | | | | | | | | | | | | | | | | | -Moved ACR interface headers from acr_gm20b.h/acr_gp106.h to Its specific header files under “drivers/gpu/nvgpu/include/nvgpu/acr/” Folder. - nvgpu_acr.h - Top-level header-file which include ACR interfaces headers & defines required to communicate with ACR, including this header file is good to get access into ACR interface & made changes accordingly, -Deleted acr.h & acr_t18x.h as not required anymore & removed its include from dependent files. Jira NVGPU-19 Change-Id: Ie404043cfe1ab32404eb63a43831f470d8436324 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304748 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use common nvgpu mutex/spinlock APIsDeepak Nibade2017-02-22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Prune gp106 clock gating listTerje Bergstrom2017-02-17
| | | | | | | | | | | | | Further prune registers that do not exist on gp106 that were not caught by previous patch. Bug 200256272 Change-Id: Ic8d6835d8726d850860d680dd1807e8020010a29 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry-picked from commit c1c9029b9b851652d7b62a96373d7c1636f3ad89) Reviewed-on: http://git-master/r/1306330 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Generalize BIOS codeTerje Bergstrom2017-02-17
| | | | | | | | | | | | | | | | | | Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Remove ACR gm204/gm206 supportMahantesh Kumbar2017-02-15
| | | | | | | | | | | | | | | | - Remove ACR gm204/gm206 support as no more support required Maxwell dGPU. -Moved required ACR interface to gp106 from gm206 -Deleted acr_gm206.c/h files & removed its involvement from dependent files. Change-Id: I9cb7ce8f7ef8bb6fcc7515e644ffb11b774389f4 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304556 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove PMU gm204/gm206 supportMahantesh Kumbar2017-02-15
| | | | | | | | | | | | | | -Created new methods for PMU gp106 whichever dependent on gm206. -Deleted pmu_gm206.c/h files & removed its involvement from dependent files. Change-Id: Ic578da53bff362efb3e142962275227787206233 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1304492 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add NVGPU_IOCTL_CHANNEL_SET_BOOSTED_CTXPeter Boonstoppel2017-02-14
| | | | | | | | | | | | | | | | This ioctl can be used on gp10b to set a flag in the context header indicating this context should be run at elevated clock frequency. FECS ctxsw ucode will read this flag as part of the context switch and will request higher GPU clock frequencies from BPMP for the duration of the context execution. Bug 1819874 Change-Id: I84bf580923d95585095716d49cea24e58c9440ed Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-on: http://git-master/r/1292746 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Organize semaphore_gk20a.[ch]Alex Waterman2017-02-13
| | | | | | | | | | | | | | | | | | | | | | | Move semaphore_gk20a.c drivers/gpu/nvgpu/common/ since the semaphore code is common to all chips. Move the semaphore_gk20a.h header file to drivers/gpu/nvgpu/include/nvgpu and rename it to semaphore.h. Also update all places where the header is inluced to use the new path. This revealed an odd location for the enum gk20a_mem_rw_flag. This should be in the mm headers. As a result many places that did not need anything semaphore related had to include the semaphore header file. Fixing this oddity allowed the semaphore include to be removed from many C files that did not need it. Bug 1799159 Change-Id: Ie017219acf34c4c481747323b9f3ac33e76e064c Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284627 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Organize nvgpu_common.[ch]Alex Waterman2017-02-13
| | | | | | | | | | | | | | | | Move nvgpu_common.c to drivers/gpu/nvgpu/common since it is a common C file to all drivers. Similarly move nvgpu_common.h to drivers/gpu/nvgpu/include/nvgpu since this follows the new include guidelines. Bug 1799159 Change-Id: I00ebed289973b27704c2cff073526e36505bf699 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1284612 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
* gpu: nvgpu: Add enable/disable shadow ROM HALTerje Bergstrom2017-02-13
| | | | | | | | | Add HAL for enabling and disabling shadow ROM. This removes XVE dependency from bios code. Change-Id: Icafec72dae71669376bbfb97077661b7165badb8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302223
* gpu: nvgpu: enable PCI MSI interruptsDavid Nieto2017-02-08
| | | | | | | | | | | | | | Use MSI interrupts instead of legacy on PCIe dGPUs to reduce latency and contention with other PCIe devices JIRA EVLR-986 Change-Id: I6cecc7e62e5797860d42a5bee21e8f4f664e1b18 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291758 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Prune clock gating listTerje Bergstrom2017-01-31
| | | | | | | | | | | | Prune from clock gating list the entries that target units that do not exist on gp106. Change-Id: I192219a24d8e67de7c1fc25276dfcccbe041a05f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1294819 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
* gpu: nvgpu: Propagate pmu initialization failuresDavid Nieto2017-01-31
| | | | | | | | | | | | | | | | | During testing it was detected that a failure in loading the firmware for the driver would not propagate, allowing some function pointers to be left unitialized. This would cause a kernel-crash later on. Bug 1866370 Change-Id: I66056a1d99229d10635293d4c1685f596f197255 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1295376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable ECC sysfs in GP106David Nieto2017-01-26
| | | | | | | | | | | | | | The current wiring causes an attempt to re-create the stats on dGPU re-bind bug 1816516 Change-Id: Idb9aea08c9f80325f6ce860b2e0e482e42e973f8 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1291822 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GPU reset for gp106 XVEAlex Waterman2017-01-24
| | | | | | | | | | | | | | | | | | Resets the GPU without resetting the XVE/XP interfaces. This allows the GPU to stay attached to the PCI bus but still resets all the rest of the GPU's internal state. Bug 1816516 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1287644 Reviewed-on: http://git-master/r/1287650 (cherry picked from commit c14efaee5d03a053d5bf229425a7594e1c6bfad0) Change-Id: If7aba3cc8109e30bd6b6aa145836e812d50b35c5 Reviewed-on: http://git-master/r/1292699 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL to get current pstateMahantesh Kumbar2017-01-17
| | | | | | | | | | | | | | | | | | - Added HAL support to get current pstate from clk_arb Note - This function is inherently unsafe to call while arbiter is running arbiter must be blocked before calling this function JIRA DNVGPU-165 Change-Id: I4e9f5eba7739280bddd9ee661fd314288c129516 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1286378 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gp106 HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: pg stat read updateMahantesh Kumbar2017-01-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Added struct pmu_pg_stats_data to extract data from multiple version of pmu pg statistics - Added pmu_pg_stats_v2 interface to fetch PG statistics data from PMU - Added MSCG debugfs node to read mscg statistics from PMU. - Added pmu_elpg_statistics HAL support for gp106 PG statistics read. - Made changes to gp104/gp106 pmu_elpg_statistics HAL to support for struct pmu_pg_stats_data JIRA DNVGPU-165 Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1252798 (cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd) Reviewed-on: http://git-master/r/1271615 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Add thermal alert limit IOCTL for UMDLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | Added the thermal alert lmit IOCTL for UMD JIRA DNVGPU-130 Bug 200231080 Change-Id: I43a3a5df18467e05c32d043f49440d2086438ebe Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1249490 (cherry picked from commit b4123e45956bd02994fd284e8bfd6ce015aa0867) Reviewed-on: http://git-master/r/1282082 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add thermal alert event handlingLakshmanan M2017-01-10
| | | | | | | | | | | | | | | | * Added the thermal alert event handling * Added the thermal alert event PMU RPC JIRA DNVGPU-130 Bug 200231080 Change-Id: I54ab0dc35a940e70733238fd95669db28389619a Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1248968 (cherry picked from commit a20593c89a374d64201e4720552160a65533ecc3) Reviewed-on: http://git-master/r/1282076 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: add read and ioctl for eventsThomas Fleury2017-01-06
| | | | | | | | | | | | | | | Add support for poll/read/ioctl for events in clock arbiter. Jira DNVGPU-186 Change-Id: Id95264fffae2b83a388ff8f186ebe7d723029b7f Reviewed-on: http://git-master/r/1253659 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> (cherry picked from commit 8d652a7313722aab331f82f0841b490ca25cb51d) Reviewed-on: http://git-master/r/1280885 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Implement SET_RD_COALESCETerje Bergstrom2017-01-05
| | | | | | | | | | | | | Implement SW method SET_RD_COALESCE to implement correct handling of texture read coalescing. Bug 200223870 Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1271303 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement permanent disable_aspmAlex Waterman2017-01-04
| | | | | | | | | | | | | | Implement the permanent disable_aspm() function for XVE on gp106. Bug 200256272 Change-Id: I63338415542381d8a43d746d9d4404a74a5f01cd Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1263273 (cherry picked from commit 7890419f242a50c6d8ec27c3e8eb331823230ed9) Reviewed-on: http://git-master/r/1280309 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: FECS trace support on gp106Thomas Fleury2017-01-04
| | | | | | | | | | | | | Enable FECS ctxsw tracing for gp106. Ensure that FECS records have been written to memory before accessing the ring. Update read index only once all records have been processed. Jira EVLR-424 Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1258243 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: RPPG supportMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Added rppg module to init GR/MS-RPPG. mscg is dependent on gr-rppg & without gr-rppg engage mscg does not engage. - Update pg engines HAL to return supported pg engines & its sub features JIRA DNVGPU-71 Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247486 (cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9) Reviewed-on: http://git-master/r/1270762 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: arb: fix rounding in effective clocksDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | Current code cast casting the frequency to 16 bit before division, giving out incorrect data JIRA DNVGPU-164 Change-Id: I4eb1fa73fb9e8963f550d3d853db39b49b990fa4 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251663 (cherry picked from commit c0d91a054f8278af9a2383bb3f837465779132a9) Reviewed-on: http://git-master/r/1274546 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: cap minimum gpc clocks to HW limitsDavid Nieto2016-12-27
| | | | | | | | | | | | | | | JIRA: DNVGPU-180 Change-Id: I1928e77cea4ac87bf2ba2b6b7b2f2942dfb97de9 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1251493 (cherry picked from commit 7b8a105652a3169d9ec0cb7ce52c3b92e42ca310) Reviewed-on: http://git-master/r/1274545 Reviewed-by: Automatic_Commit_Validation_User Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: keep sec2 idleMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | | sec2 falcon reset after secure boot complete to keep sec2 idle issue: ELPG does not engage if PG engine is dependent on sec2 idleness JIRA DNVGPU-71 Change-Id: If264c610dae857ae9b9f9bc77c59f24f239ce1ce Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247290 (cherry-picked from commit de2337de1211e4167993982e50237fe1115053a1) Reviewed-on: http://git-master/r/1267260 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 14:41:27 -0400