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* gpu: nvgpu: handle vf curve change due to tempVijayakumar2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-129 1)send 150'c as default temperature to PMU so that PMU will start reading temperature from sensor to evaluate VFE equations 2)Send GP106's temp min and max range for GPU sensor so that PMU will read right temperature 3)PMU will send event whenever temperature goes above +ve hysteresis or goes below -ve hysteresis. Call the Arbiter's VF re-evaluation function in the event handler. Change-Id: Iaebc0655f60e17998f0864824095f4fc8bba5b62 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245392 (cherry picked from commit 7e59d0faa8cee6aace5524c724001e88248b2da7) Reviewed-on: http://git-master/r/1268062 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Tested-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: resolve signed/unsigned mismatchDavid Nieto2016-12-27
| | | | | | | | | | | JIRA DNVGPU-143 Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1268107 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: get voltage, current, power and temperatureThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | Add ioctls to retrieve voltage, current, power and temperature. Add flags in GPU characteristics to indicate if feature is supported. Jira DNVGPU-166 Change-Id: Ifaafe2efdb6b09d7b28215b641814f28e894151e Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1241861 Tested-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1267122
* gpu: nvgpu: gpu: read effective frequence from counterDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | (1) modified counters debug code to export to the driver (2) modified arbiter to read from those functions (3) modified counter for higher accuracy on MHz range JIRA DNVGPU-164 Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239467 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1268008
* nvgpu: gpu: arbiter for vf switch managementDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Use bootstrap base for WPR addressTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | Use the bootstrap base address for calculating the address of WPR. The bootstrap base is dynamic and depends on amount of memory, so we should not hard code any address. Bug 200244445 Change-Id: Ia700d24c8d572a25946f7b1847faec72c40c6796 Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1242252 Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-on: http://git-master/r/1267125 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clk requests completion and event fdsThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | Install one completion fd per SET request. Notifications on dedicated event fd. Changed frequencies unit to Hz from MHz. Remove sequence numbers from dummy arbiter. Added effective clock type (query frequency from counters). Jira DNVGPU-125 Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1230239 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560) Reviewed-on: http://git-master/r/1243106
* gpu: nvgpu: clk arbiter skeletonThomas Fleury2016-12-27
| | | | | | | | | | | | | | | | | | | | Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: correct adc slope ofset sign bitVijayakumar2016-12-27
| | | | | | | | | | | | | | bug 1838549 Change-Id: I40457aebd49a02d0dd54d6dc9c965f89613ee21f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1251371 (cherry picked from commit 2c80f36830baf48bab043d7f1ebbcbe7759789c4) Reviewed-on: http://git-master/r/1251452 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add FBPA base addressesPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add FBPA base addresses Bug 200249125 Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1247802 (cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a) Reviewed-on: http://git-master/r/1252163 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Program RX bias currentTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Hard code RX bias current to 0x2. Bug 1833830 Change-Id: I1107bad52de7b38d311bc5795739777a4bb4239a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1253656 (cherry picked from commit 7e853b0c62043cc53847e3535e05886d574dc779) Reviewed-on: http://git-master/r/1255724 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp10x: updated API for get_litter_valueseshendra Gadagottu2016-12-27
| | | | | | | | | | | | | get_litter_value API is updated to use int instead of enum type. JIRA GV11B-21 Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1252212 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix signed comparison bugsTerje Bergstrom2016-12-27
| | | | | | | | | | | | Fix small problems related to signed versus unsigned comparisons throughout the driver. Bump up the warning level to prevent such problems from occuring in future. Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1252069 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gp106: Add regops whitelistsPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | Add regops whitelists for gp106. The whitelist is generated, and is the same for context switched and global registers. Bug 200239422 Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1243253 (cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db) Reviewed-on: http://git-master/r/1247645 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Free pmu_sig if init PMU failsTerje Bergstrom2016-12-27
| | | | | | | | | | | If gk20a_init_pmu() fails, go to the error path that frees pmu_sig. Change-Id: I2f6fcb86570aba54ab45aec14ee6f341e3faebd5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: Return correct GPC base addressesTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Due to missing break statements, GPC base and GPC shared base were overwritten by values in following select cases. Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249970 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com>
* gpu: nvgpu: gp106: Add PMU HAL is_pmu_supportedTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Add implementation for PMU HAL is_pmu_supported to gp106. JIRA GV11B-21 Change-Id: If4268465ffade7c3c8e7bb853a1d2070c0e2ae4f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1246026 Tested-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Update volt pwm source & raw periodMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | - calculate raw period as per pwm source - update pwm source for logic & sram rails. JIRA DNVGPU-123 Change-Id: I50b41d51b6aba760710700522dced7859f815463 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1227626 (cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4) Reviewed-on: http://git-master/r/1244663 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: At FB reset wait for scrubberTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | We need to wait for scrubber to have finished before we can allow any accesses to memory. Do the wait in place where on iGPU we would do FB reset. Bug 1799537 Bug 1815139 Change-Id: Ic92dee936388a13c4abf0b295fd99581522c430f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1235541 (cherry picked from commit 1ef73ecb4e37da042e7117426ab2823b7f4528dc) Reviewed-on: http://git-master/r/1239955 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix sparse warning in LTC codeDavid Nieto2016-12-27
| | | | | | | | | | | | bug 200088648 sparse warning reported that the function was not defined. This was due to a missing include Change-Id: Ia6153a2f3348a86e78add95bcfff998505b47cdd Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1237845 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: parse and execute mclk shadow scriptDavid Nieto2016-12-27
| | | | | | | | | | | | | * Parsing of shadow registers from VBIOS * Partial devinit engine interpreter implementation JIRA DNVGPU-117 Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1214956 Reviewed-on: http://git-master/r/1237293 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move ELCG programming to thermTerje Bergstrom2016-12-27
| | | | | | | | | | | | | Implement gp10b and gp106 ELCG programming. JIRA DNVGPU-74 Change-Id: Ic0349b948a2870e0d39e95ddd2f49231e7b4cbe0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1220431 (cherry picked from commit d6bc48647982babdf642ea6004d4208c5daa243f) Reviewed-on: http://git-master/r/1239422 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add accessors for invalid ctx_statusDeepak Nibade2016-12-27
| | | | | | | | | | | Bug 1826768 Change-Id: I8be2b9c074868206cb95b3bc84d66ea84683b19a Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1237522 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Cory Perry <cperry@nvidia.com>
* gpu: nvgpu: implement PCIe Gen2 frequency swapAlex Waterman2016-12-27
| | | | | | | | | | | | | | | | | | | | Implement the basic code to swap between PCIe bus speeds for the GPU. Other GPUs are not supported yet. Currently the following speeds can be used: Gen1 (2.5 MTPS) Gen2 (5.0 MTPS) gp106 on DPX2 does not support Gen3. JIRA DNVGPU-89 Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499 Reviewed-on: http://git-master/r/1218177 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1227925 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp10x: Add debugfs entry for temperature readingLakshmanan M2016-12-27
| | | | | | | | | | | | | | | Added current temperature reading support for gp10x. JIRA DNVGPU-48 Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1213717 (cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b) Reviewed-on: http://git-master/r/1234092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Suppress error msg from VBIOS overlayTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | | | | | | Suppress error message when nvgpu tries to load VBIOS overlay, but one is not found. This situation is normal. This is done by moving gk20a_request_firmware() to be nvgpu generic function nvgpu_request_firmware(), and adding a NO_WARN flag to it. Introduce also a NO_SOC flag to suppress attempt to load firmware from SoC specific directory in addition to the chip specific directory. Use it for dGPU firmware files. Bug 200236777 Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1223839 (cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d) Reviewed-on: http://git-master/r/1233412 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: MCLK P8/P5 sequences and APIDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | Adds P5/P8 sequences and simple debugfs API to change from P0->P5 JIRA DNVGPU-117 Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1208655 (cherry picked from commit dd410a86263e2407e043743945cf09a77910d745) Reviewed-on: http://git-master/r/1231035 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update PMU bootloader paramsMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | | | | | | - Bootloader of PMU is changed & bootloader takes params using flcn_bl_dmem_desc_v1 descriptor to boot PMU JIRA DNVGPU-116 Change-Id: I005b615b2323678fa605d190c6b9b629976f0b74 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212818 (cherry picked from commit 89976a03c13cce6bbba25c99270b0da4ca0f2441) Reviewed-on: http://git-master/r/1223842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add gp106 clock gating tablesTerje Bergstrom2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-72 JIRA DNVGPU-73 Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1215915 (cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390) Reviewed-on: http://git-master/r/1227267 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: gp106: Skip resetting FBTerje Bergstrom2016-12-27
| | | | | | | | | | | | | FB is enabled in devinit. Skip resetting it in GPU boot. Bug 1799537 Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208715 (cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698) Reviewed-on: http://git-master/r/1227265 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: add debugfs to dump clocksDavid Nieto2016-12-27
| | | | | | | | | | | | | | | | | * Removed unused registers from headers * Added counter based MCLK * Removed hardcoding JIRA DNVGPU-98 Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1204019 (cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c) Reviewed-on: http://git-master/r/1227264 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add dGPU clocks supportVijayakumar Subbu2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Adding support for mclk moduleMahantesh Kumbar2016-12-27
| | | | | | | | | | | | | JIRA DNVGPU-88 Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1202551 (cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108) Reviewed-on: http://git-master/r/1223854 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Add NVC097_SET_GO_IDLE_TIMEOUT SW methodSami Kiminki2016-12-27
| | | | | | | | | | | | | | | Add the NVC097_SET_GO_IDLE_TIMEOUT SW method for GP106. This enables booting the X server. Bug 1732372 Bug 1792002 Change-Id: I73abaaea240039dc91c66e3862ec01a342db2fa9 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1200637 (cherry picked from commit 0d24a6f3d8e421ea5205279166c6dc2d0f15c6a0) Reviewed-on: http://git-master/r/1223101 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select target based on apertureDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | | | | | | For bar2 and pmu instance blocks, use gk20a_aperture_mask() to select target address (i.e. if address is in sysmem or vidmem) based on aperture Also add target accessors for gr_fecs_new_ctx and gr_fecs_arb_ctx_ptr Jira DNVGPU-22 Change-Id: Ieaa80bd83a4191fe57b7fba6e0f9cdaeb195a077 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1216138 (cherry picked from commit 7a9f4175abc5dddf0879215de4637b7b6eb0ab7b) Reviewed-on: http://git-master/r/1219712 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Skip LTCA initializationTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | Skip LTCA initialization on dGPU. Bug 1799537 Change-Id: Ieb4c72e2169dc6bee73306c9b1e6c80866167a1a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208714 (cherry picked from commit 9a8dc5fe96b29b8a67f8203f17126b0093721312) Reviewed-on: http://git-master/r/1219164 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Do not initialize CBC on Pascal dGPUTerje Bergstrom2016-12-27
| | | | | | | | | | | | | CBC_BASE register is protected on Pascal dGPUs. Skip initializing it. Bug 1799537 Change-Id: Ie4b0ac5a37c3c586d1b631ce38823d156b554e1e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208016 (cherry picked from commit 5f9dbca140573798bd05b5b27a7b6abe1871e90f) Reviewed-on: http://git-master/r/1210289 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: fix cbc base calculation for dGPUDavid Nieto2016-12-27
| | | | | | | | | | | | JIRA DNVGPU-9 Change-Id: I22667acfadfcabf79af841ca5389e41d2ac34860 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1206478 (cherry picked from commit 098b932f7633a903c915b1257beb9304735b4113) Reviewed-on: http://git-master/r/1210288 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gp106: Remove clock gating prod valsTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | | We are using gp10b prod values for gp106, and they are incompatible. Because of this we are accessing invalid registers. Delete all prod vals for gp106 until we have generated new ones. Bug 1799537 Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208716 (cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804) Reviewed-on: http://git-master/r/1217287 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: vgpu: cyclestat snapshot supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | Add support for cyclestats snapshots in the virtual case Bug 1700143 JIRA EVLR-278 Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1216644 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: check if pmu blob is already allocatedDeepak Nibade2016-12-27
| | | | | | | | | | | | Jira DNVGPU-20 Change-Id: If917f97ee30f830b05467b15e1ae3f8be296d140 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1206406 (cherry picked from commit bc54e4c24d2f2671b412c79a0ff2944c9575f2a5) Reviewed-on: http://git-master/r/1210961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: use bootstrap base for WPRDeepak Nibade2016-12-27
| | | | | | | | | | | | | | | Use bootstrap allocator's base as base address for WPR buffers Jira DNVGPU-84 Change-Id: Ifaeef9f3aa562f9171dd073000c158b513567ede Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1201348 (cherry picked from commit 72f8e727e6f27f867043d024e3d07218359d5faf) Reviewed-on: http://git-master/r/1210960 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Skip initializing thermals on dGPUTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | On dGPU devinit handles initializing thermals. Bug 1799537 Change-Id: I12ade535d2ddb7fc406256e75f21a422195b36d5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208017 (cherry picked from commit 0e1327107c43dc9c2f5c5d9b79a54f27d2027e85) Reviewed-on: http://git-master/r/1209122 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: ppc register supportPeter Daifuku2016-12-27
| | | | | | | | | | | | | | | | | Fix support for ppc_in_gpc_base Add support for ppc_in_gpc_shared_base Bug 1771830 Change-Id: I3c4576c4d9233ec05f9a52952f42e3226532ff5b Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1201509 (cherry picked from commit 8594628ad4cb90e3298b0d1a3f94aeb50d9c27ab) Reviewed-on: http://git-master/r/1203183 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: move dbg_session_ops to gopsPeter Daifuku2016-12-27
| | | | | | | | | | | | | | Move dbg_session_ops to gops for better code consistency JIRA VFND-1905 Change-Id: I0ac10a69194c8ca485f361cd8cea61d8ab72145a Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1192642 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Add preemption mode support for gp10xLakshmanan M2016-12-27
| | | | | | | | | | | | | | Added preemption mode (WFI, GFXP, CTA and CILP) support for gp10x family gr class (PASCAL_B and PASCAL_COMPUTE_B). Bug 200221149 Change-Id: Ia8b781c5baedba660db5997f190a0b363286ed7f Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1193209 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: unset get_phys_addr_bits for dGPUThomas Fleury2016-12-27
| | | | | | | | | | | | | | | Unset get_phys_addr_bits as PCIe devices do not need to care if SMMU is enabled or not. Jira VFND-1965 Change-Id: Ice87ff06087ec6c0a123dcf054717eff80acc8f9 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1183085 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: gp106: reserve wpr from allocatorKonsta Holtta2016-12-27
| | | | | | | | | | | | | | | | | | In addition to nonwpr_base address, allocate also the wpr_base that is configured as wpr, in order to not overlap user allocations on that area. Jira DNVGPU-18 Change-Id: Ie2976a091e8084fcdc8ffd9fb4b6c75411450acb Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/1182874 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Fix read_ptimer hook for GP106Sami Kiminki2016-12-27
| | | | | | | | | | | | | | | | Add the read_ptimer hook for GP106. This makes NVGPU_GPU_IOCTL_GET_GPU_TIME not crash on call. Bug 1787348 Change-Id: I31d7c30bcf0d6ad7fdecccd25a7c9c16276632a2 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/1179661 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Disable init_preemption_state on dGPUTerje Bergstrom2016-12-27
| | | | | | | | | | | | | | | | Discrete GPU does not have clocks wired correctly. They're needed to be able to calculate correct preemption timeout, so disable setting the timeout. Change-Id: I14a6d262f6b004d40432a4e026c5558303aa90a4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1176904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 15:32:31 -0400