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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
pmu sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8839ac99e87153637005e23b3013237f57275c54
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530982
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525713
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.
- Created ops to do PMU engine reset & to
know the engine reset status
- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)
- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.
JIRA NVGPU-99
Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gp106_pmu_elpg_statistics() can be re-used by other chips.
The function is changed to non-static & exposed outside
gp106 scope.
Bug 200305607
Change-Id: I4ba660509ce816bebc59855227a8d409ed8f84f8
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1476005
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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secure PMU reset i.e. gp106_pmu_reset() is changed
to a non-static function, so that it can be re-used
outside gp106 scope.
Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for chips gp104 and gp106.
Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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