| Commit message (Collapse) | Author | Age |
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Move non-function pointer members out of the pmu and pmu_ver
substructs of gpu_ops. Ideally gpu_ops will have only function
ponters, better matching its intended purpose and improving
readability.
- g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to
g.pmu_ver_cmd_id_zbc_table_update
- g.ops.pmu.lspmuwprinitdone has been changed to
g.pmu_lsf_pmu_wpr_init_done
- g.ops.pmu.lsfloadedfalconid has been changed to
g.pmu_lsf_loaded_falcon_id
Boolean flags have been implemented using the enabled.h API
- g.ops.pmu_ver.is_pmu_zbc_save_supported moved to
common flag NVGPU_PMU_ZBC_SAVE
- g.ops.pmu.fecsbootstrapdone moved to
common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE
Jira NVGPU-74
Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530981
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525713
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.
JIRA NVGPU-93
Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move mclk related functions be moved to clk structure instead of
pmu. We want to keep pmu only for basic pmu interaction and
split clk, lpwr etc.
Bug 1921094
Change-Id: I32394bc0e6d3657dfbd34dbcf19c9af56c12e194
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master/r/1506586
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove mem_config_idx from platform data, and instead let
HAL determine which memory configuration to use. For this
purpose, HAL may use PCI device identifiers, VBIOS version
and possibly RAMCFG strap register.
Bug 1929155
Change-Id: I6633e9e0c79728c8e3740f3f956b53b3abfc667b
Reviewed-on: http://git-master/r/1497812
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit b7141ff5441b7ea95f9826eb37ae869f408e1414)
Reviewed-on: https://git-master/r/1506584
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.
- Created ops to do PMU engine reset & to
know the engine reset status
- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)
- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.
JIRA NVGPU-99
Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- replace usage of pmu_copy_from_dmem() with
nvgpu_flcn_copy_from_dmem()
- delete nvgpu_flcn_copy_from_dmem()
JIRA NVGPU-99
Change-Id: If0919187078f95a165d6a152f180549ac121beaa
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1506534
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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FECS override PMU support was removed with http://git-master/1297370.
Remove the sysfs API that is wired to that.
Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507934
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- set nvgpu_flcn_reset() to point to gk20a_pmu_reset()
- set PMU interrupt using nvgpu_flcn_enable_irq()
- replace pmu_idle with nvgpu_flcn_wait_idle()
JIRA NVGPU-57
Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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linux/version.h and linux/sched.h are not used by gk20a.h, so remove
them.
acr_gm20b.h and bus_gk20a.h are not needed by gk20a.h, so remove them.
pmu_gp106.c relies on implicit #include of acr_gm20b.h by gk20a.h, so
add that as an explicit #include.
Remove #include of iomap.h. platform_gk20a_tegra.c legacy rail gating
code still relies on access to that header, so add it as explicit
include.
JIRA NVGPU-38
Change-Id: I1cf57b9d3a7ee5e3cad298341107e317b4b8662f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505926
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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move mclk switching to gp106 hal.
Bug 1921082
JIRA EVLR-1269
Change-Id: I97812b871384460bec88fddac0f6a326df12fc45
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1499393
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Moved PMU init code from pmu_gk20a.c to
"drivers/gpu/nvgpu/common/pmu/pmu.c" file
- Moved below related methods
SW/HW init,
init msg handler,
deinit/destroy,
PMU state machine
-Created HAL methods to read message queue tail
& supported mutex count.
-prepend with nvgpu_ for pmu init global
mehtods
JIRA NVGPU-56
JIRA NVGPU-92
Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1480002
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Moved PMU IPC related code to
drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file,
-Below is the list which are moved
seq
mutex
queue
cmd/msg post & process
event handling
NVGPU-56
Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1478167
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved
to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/"
- Included header file "pmu.h" to dependent file &
removed "pmu_gk20a.h" include if its usage is not present.
- Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent
source & header files.
JIRA NVGPU-56
Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1479209
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gp106_pmu_elpg_statistics() can be re-used by other chips.
The function is changed to non-static & exposed outside
gp106 scope.
Bug 200305607
Change-Id: I4ba660509ce816bebc59855227a8d409ed8f84f8
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1476005
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I54db15d9abf578ec334b100635baec214fe22af5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460116
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: I18955b4c46c082883ee0bf589ab17cd66ab0add2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457346
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- check return value of nvgpu_mutex_init in clk_mclk.c
- declare new callback g->ops.pmu.mclk_deinit() to
deinitialize mclk mutexes
- and define this callback for gp106
- add corresponding nvgpu_mutex_destroy calls in
deinitialization
Jira NVGPU-13
Change-Id: I1491c084d330ac9756c9520477e6fe494560e651
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1321294
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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secure PMU reset i.e. gp106_pmu_reset() is changed
to a non-static function, so that it can be re-used
outside gp106 scope.
Change-Id: I7d4c4ec6ca1bd315bf8c681723fb350277103c3b
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1303758
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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-Created new methods for PMU gp106 whichever dependent
on gm206.
-Deleted pmu_gm206.c/h files & removed its involvement
from dependent files.
Change-Id: Ic578da53bff362efb3e142962275227787206233
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304492
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.
JIRA GV11B-30
Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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HAL to query LPWR feautre's RPPG/MSCG support
based on current pstate configured.
JIRA DNVGPU-71
Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1283916
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Move the gp106 HW headers to a new directory specially for them:
include/nvgpu/hw/gp106
And change the code to include like so:
#include <nvgpu/hw/gp106/hw_fb_gp106.h>
This is part of the process to restructure the nvgpu driver.
Bug 1799159
Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280327
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Added struct pmu_pg_stats_data to extract
data from multiple version of pmu pg statistics
- Added pmu_pg_stats_v2 interface to fetch
PG statistics data from PMU
- Added MSCG debugfs node to read mscg
statistics from PMU.
- Added pmu_elpg_statistics HAL support for
gp106 PG statistics read.
- Made changes to gp104/gp106
pmu_elpg_statistics HAL to support
for struct pmu_pg_stats_data
JIRA DNVGPU-165
Change-Id: I2b9e89c0fae90deb45006c4478170b9a97b56603
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1252798
(cherry picked from commit 3c073b15fd991db8d65b3171b02c161294be40cd)
Reviewed-on: http://git-master/r/1271615
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- Added rppg module to init GR/MS-RPPG.
mscg is dependent on gr-rppg & without
gr-rppg engage mscg does not engage.
- Update pg engines HAL to return supported
pg engines & its sub features
JIRA DNVGPU-71
Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247486
(cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9)
Reviewed-on: http://git-master/r/1270762
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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- Updated gp10b_pg_gr_init() to post init param based
on PG engine parameter
- Assigned pg engine list/features HAL to respective
functions/NULL
JIRA DNVGPU-71
Change-Id: I7d059796746694b22800c6ae0327cbc90331e929
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247407
(cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502)
Reviewed-on: http://git-master/r/1269321
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add implementation for PMU HAL is_pmu_supported to gp106.
JIRA GV11B-21
Change-Id: If4268465ffade7c3c8e7bb853a1d2070c0e2ae4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1246026
Tested-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Adds P5/P8 sequences and simple debugfs API to
change from P0->P5
JIRA DNVGPU-117
Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1208655
(cherry picked from commit dd410a86263e2407e043743945cf09a77910d745)
Reviewed-on: http://git-master/r/1231035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-88
Change-Id: Idecfff5a80fadde77887385491dd6b73b1956bac
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1202551
(cherry picked from commit 3bcf9bad93fb6fdd4b87430b346ea41533149108)
Reviewed-on: http://git-master/r/1223854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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nvgpu/gp106/pmu_gp106.c:30:5: warning: symbol
'gp106_pmu_enable_hw' was not declared. Should it be static?
nvgpu/gp106/pmu_gp106.c:118:5: warning: symbol
'gp106_pmu_reset' was not declared. Should it be static?
nvgpu/gp106/pmu_gp106.c:146:5: warning: symbol
'gp106_sec2_reset' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:79:6: warning: symbol
'gp106_wpr_info' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:92:5: warning: symbol
'gp106_alloc_blob_space' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:120:5: warning: symbol
'pmu_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:187:5: warning: symbol
'fecs_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:265:5: warning: symbol
'gpccs_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:348:5: warning: symbol
'gp106_prepare_ucode_blob' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:1011:5: warning: symbol
'gp106_bootstrap_hs_flcn' was not declared. Should it be static?
Bug 200088648
Change-Id: I13716e39f540f8674b1c0f917048bb6b63f7b763
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1173076
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Enable OPS to support secure boot
- PMU/SEC2 reset sequence change for GP104/GP106
JIRA DNVGPU-34
Change-Id: I583a6af1d5354649c3df9d9b4d74141d52d6ca9d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1161132
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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fix below sparse warning :
$TOP/kernel-nvgpu-t18x/drivers/gpu/nvgpu/gp106/pmu_gp106.c:22:5:
warning: symbol 'gp106_pmu_reset' was not declared. Should it be static?
Bug 200088648
Change-Id: I86120fb6b9733f256c96764a77c6ea4bb636934a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1154452
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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Add support for chips gp104 and gp106.
Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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