| Commit message (Collapse) | Author | Age |
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Add support for poll/read/ioctl for events in clock
arbiter.
Jira DNVGPU-186
Change-Id: Id95264fffae2b83a388ff8f186ebe7d723029b7f
Reviewed-on: http://git-master/r/1253659
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit 8d652a7313722aab331f82f0841b490ca25cb51d)
Reviewed-on: http://git-master/r/1280885
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Enable FECS ctxsw tracing for gp106. Ensure that FECS records
have been written to memory before accessing the ring. Update
read index only once all records have been processed.
Jira EVLR-424
Change-Id: I1a21f841fcce1588397408906d77e2c3bf4a8c01
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1258243
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add ioctls to retrieve voltage, current, power and temperature.
Add flags in GPU characteristics to indicate if feature is supported.
Jira DNVGPU-166
Change-Id: Ifaafe2efdb6b09d7b28215b641814f28e894151e
Signed-off-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1241861
Tested-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1267122
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Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add FBPA base addresses
Bug 200249125
Change-Id: I235fa12a00ef2c5b2f0415bb18755523e8a2754b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1247802
(cherry picked from commit d2c73ee989d3abeae305ff68ab355772c5e0af5a)
Reviewed-on: http://git-master/r/1252163
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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get_litter_value API is updated to use int instead of
enum type.
JIRA GV11B-21
Change-Id: I982fdfe372f4be38aa4ed026a23e936d73190e79
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1252212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add regops whitelists for gp106. The whitelist is generated, and is the
same for context switched and global registers.
Bug 200239422
Change-Id: Ib6689956c191c8f346da8cc5c7e3791f105db4eb
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1243253
(cherry picked from commit 1bdc23c9f9aac7ba91a50b83397925237851f8db)
Reviewed-on: http://git-master/r/1247645
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Due to missing break statements, GPC base and GPC shared base were
overwritten by values in following select cases.
Change-Id: Iba50d8256c1cf07ff8e631e2fcf22a68cdc992e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1249970
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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* Parsing of shadow registers from VBIOS
* Partial devinit engine interpreter implementation
JIRA DNVGPU-117
Change-Id: I42179748889f17d674ad0a986e81c418b3b8df11
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1214956
Reviewed-on: http://git-master/r/1237293
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Implement the basic code to swap between PCIe bus speeds for the GPU.
Other GPUs are not supported yet. Currently the following speeds can
be used:
Gen1 (2.5 MTPS)
Gen2 (5.0 MTPS)
gp106 on DPX2 does not support Gen3.
JIRA DNVGPU-89
Change-Id: I8bebfc9d99b682bdcff406fa56e806097dd51499
Reviewed-on: http://git-master/r/1218177
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1227925
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added current temperature reading support for gp10x.
JIRA DNVGPU-48
Change-Id: I45959da28bbd207dcf899a9eb37900c69895cfc1
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1213717
(cherry picked from commit 805245889d1df8aefce277cff9ea31ea5fb4706b)
Reviewed-on: http://git-master/r/1234092
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-72
JIRA DNVGPU-73
Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1215915
(cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390)
Reviewed-on: http://git-master/r/1227267
GVS: Gerrit_Virtual_Submit
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FB is enabled in devinit. Skip resetting it in GPU boot.
Bug 1799537
Change-Id: I0748127f0962e7d6d2bf0ecece6773fdf9c35bc8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208715
(cherry picked from commit ceafac52f5711bd987b746686f11b22807f74698)
Reviewed-on: http://git-master/r/1227265
GVS: Gerrit_Virtual_Submit
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* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-42
Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1205850
(cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114)
Reviewed-on: http://git-master/r/1227257
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-9
Change-Id: I22667acfadfcabf79af841ca5389e41d2ac34860
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1206478
(cherry picked from commit 098b932f7633a903c915b1257beb9304735b4113)
Reviewed-on: http://git-master/r/1210288
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We are using gp10b prod values for gp106, and they are incompatible.
Because of this we are accessing invalid registers.
Delete all prod vals for gp106 until we have generated new ones.
Bug 1799537
Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208716
(cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804)
Reviewed-on: http://git-master/r/1217287
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add support for cyclestats snapshots in the virtual case
Bug 1700143
JIRA EVLR-278
Change-Id: I353efac6a17704c815a99745ac04d2c3d831351b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1216644
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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On dGPU devinit handles initializing thermals.
Bug 1799537
Change-Id: I12ade535d2ddb7fc406256e75f21a422195b36d5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1208017
(cherry picked from commit 0e1327107c43dc9c2f5c5d9b79a54f27d2027e85)
Reviewed-on: http://git-master/r/1209122
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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Fix support for ppc_in_gpc_base
Add support for ppc_in_gpc_shared_base
Bug 1771830
Change-Id: I3c4576c4d9233ec05f9a52952f42e3226532ff5b
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1201509
(cherry picked from commit 8594628ad4cb90e3298b0d1a3f94aeb50d9c27ab)
Reviewed-on: http://git-master/r/1203183
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move dbg_session_ops to gops for better code consistency
JIRA VFND-1905
Change-Id: I0ac10a69194c8ca485f361cd8cea61d8ab72145a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1192642
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add the read_ptimer hook for GP106. This makes NVGPU_GPU_IOCTL_GET_GPU_TIME
not crash on call.
Bug 1787348
Change-Id: I31d7c30bcf0d6ad7fdecccd25a7c9c16276632a2
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1179661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Bug 200214046
Change-Id: I02a2e5d13f444dbdc1b4eab51ebfda6ab9402734
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1172600
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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JIRA DNVGPU-34
Change-Id: Iea1964c7d12536591659188c8e969fc7fb632d12
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1166785
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Added fifo configuration support for gp104 and
gp106. These GPU chips have more number of
channel fifo and runlist than gp10b.
Added get_num_fifos and
eng_runlist_base_size function pointer
to find out the actual value from HW headers.
JIRA DNVGPU-25
Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1164653
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Build support & enable GPMU secure boot
for GP10x
JIRA DNVGPU-34
Change-Id: Id1316677ed44790aa150e0ada8ff39daf0ef1d0c
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1161174
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Read video memory size from hardware during initialization for devices
that support it.
JIRA DNVGPU-14
Change-Id: I84e1bca0eaac8dc204e1fb82628acc6b52c3e5cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
Pascal GPU series
5) Removed hard coded engine_id logic and
made generic way
6) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Add support for chips gp104 and gp106.
Change-Id: Ied5f239bdd0ec85245bce1fb6ef51330871d0f05
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120465
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ken Adams <kadams@nvidia.com>
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