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Current code cast casting the frequency to 16 bit
before division, giving out incorrect data
JIRA DNVGPU-164
Change-Id: I4eb1fa73fb9e8963f550d3d853db39b49b990fa4
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1251663
(cherry picked from commit c0d91a054f8278af9a2383bb3f837465779132a9)
Reviewed-on: http://git-master/r/1274546
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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JIRA DNVGPU-143
Change-Id: I0536aff4f994efc3dbd2db949068f8e1345ece9c
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1268107
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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(1) modified counters debug code to export to the driver
(2) modified arbiter to read from those functions
(3) modified counter for higher accuracy on MHz range
JIRA DNVGPU-164
Change-Id: I2bbf7c9be4dc59718d1d91c53028a39020b5aea5
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239467
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1268008
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Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent
such problems from occuring in future.
Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252069
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- calculate raw period as per pwm source
- update pwm source for logic & sram rails.
JIRA DNVGPU-123
Change-Id: I50b41d51b6aba760710700522dced7859f815463
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1227626
(cherry picked from commit 6eb5a235dd7bf9031ef1bcfadd6312a2f8758fd4)
Reviewed-on: http://git-master/r/1244663
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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