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path: root/drivers/gpu/nvgpu/gm20b
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* gpu: nvgpu: gm20b: select NETB for final NETLISTSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | Final netlist for T210 uses NETB firmware for gpu. Change-Id: Id396f1b6fa53f8d3c7b39ad0f93db230d6ad6d86 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/441355 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Store LTC configurationArto Merilainen2015-03-18
| | | | | | | | | Change-Id: Ia780e6a7cb3579f0d6ed2dca9949a349799535fd Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/448115 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL programming sequenceAlex Frid2015-03-18
| | | | | | | | | | | | | | | | Updated GM20B GPCPLL programming sequence to utilize new glitch-less post divider: - No longer bypass PLL for re-locking if it is already enabled, and post divider as well as feedback divider are changing (input divider change is still under bypass only). - Use post divider instead of external linear divider to introduce (VCO min/2) intermediated step when changing PLL frequency. Bug 1450787 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I4fe60f8eb0d8e59002b641a6bfb29a53467dc8ce
* gpu: nvgpu: Updated GM20b GPCPLL dynamic ramp setupAlex Frid2015-03-18
| | | | | | | | | | | Setup GPCPLL dynamic ramp coefficients based on update rate (instead of hard-coding), since on GM20B high reference clock 38.4MHz allows to use several update rates within supported range. Bug 1450787 Change-Id: I0e14bcb8e3f65cc164fbb66b4adc688fcee9e2d6 Signed-off-by: Alex Frid <afrid@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL locking under bypassAlex Frid2015-03-18
| | | | | | | | | | Moved GPCPLL locking under bypass procedure into separate function. Added SYNC_MODE control during locking. Bug 1450787 Change-Id: I8dbf9427fbdaf55ea20b6876750b518eb738de1b Signed-off-by: Alex Frid <afrid@nvidia.com>
* gpu: nvgpu: gm20b: update gpu headersSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Keep gm20b headers upto date with script output Change-Id: I0916df7c43616b1d9231436a512290c2fa901d64 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/447725 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL parametersAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Updated GPCPLL parameters according to GM20b specification. Modified PLL programming, since on GM20b PLL post divider value is equal to divider setting (which was not the case on GK20a this code was inherited from). Bug 1450787 Change-Id: Ia455ac49040047a3dbcd5d5211f2fbc71dc332ae Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447751 GVS: Gerrit_Virtual_Submit Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL initial configurationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | - Set initial output rate to 1/3 of VCO minimum. - Cleared global BYPASSCTRL to get ready for enabling PLL (this won't bring PLL out of bypass, since SEL_VCO register is cleared). - Added debugfs nodes for BYPASSCTRL and SEL_VCO state. Bug 1450787 Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447750 GVS: Gerrit_Virtual_Submit Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Expand GM20b PLL fields headerAlex Frid2015-03-18
| | | | | | | | | | | | | | | Added masks for GM20b GPCPLL input and post dividers. Bug 1450787 Change-Id: I39a9c7ffb740fa9ef3a614deb2591412e34ef263 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* nvgpu: new gpmu ucode compatibilitySupriya2015-03-18
| | | | | | | | | | | | | | For LS PMU new ucode needs to be used. Ucode has interface header file changes too. This patch also has fixes for pmu dmem copy failure Bug 1509680 Change-Id: I8c7018f889a82104dea590751e650e53e5524a54 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/441734 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Make clock operations staticAlex Frid2015-03-18
| | | | | | | | | | | | | Made GK20A and GM20B clock operations static, since they are invoked only via HAL interfaces. Bug 1450787 Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/441710 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Switch to use GM20B hw header filesHoang Pham2015-03-18
| | | | | | | | | | | Bug 1450787 Change-Id: Id28bd49eadae7b2310410c1676d73b37f57d1443 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/441543 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Fork GM20B clock from GK20A clockHoang Pham2015-03-18
| | | | | | | | | Bug 1450787 Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/440536 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add gm20b h/w definitionsAlex Frid2015-03-18
| | | | | | | | | | | | | Added SYNC_MODE field, and BYPASSCTRL register; expanded GPC2CLK_OUT_VCODIV field. Bug 1450787 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: Ibf2119a88b0d5f099199920e70b2e88f04b8863b Reviewed-on: http://git-master/r/440928 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: Split clk_ops for GK20A and GM20BHoang Pham2015-03-18
| | | | | | | | | | | Split clk_ops for GK20A and GM20B into different files Bug 1450787 Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/437771 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gm20b: fix CBC clearWei Sun2015-03-18
| | | | | | | | | | | | | | | gm20b_ltc_cbc_ctrl sent the wrong register value to clear the CBC. Bug 1507804 Change-Id: Ib0d867a122466e50cb15fef3b320fb2ee8455ef2 Signed-off-by: Wei Sun <wsun@nvidia.com> Reviewed-on: http://git-master/r/435297 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Exclude non-secure boot with CONFIG_TEGRA_ACRSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Do not compile non-secure boot code if CONFIG_TEGRA_ACR is defined. Bug 1524197 Change-Id: Id1ec222e00e2229e1d28e406e4ddad99e368296e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/433356 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* nvgpu: Modify ACR host to use physical trancfgSupriya2015-03-18
| | | | | | | | | | | | | | | | | PMU ucode and ACR ucode need 0th ctx dma to be programmed for Physical access. To stay in sync with ucodes, modified 0th transcfg to be physical access, and suitably modified all other ctx dma's sent. Bug 1509680 Change-Id: Ib3a24ebb8478488af57bb465d782e4045ca7d0d0 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/432084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: Fix definition of cbc_ctrl1 registersTerje Bergstrom2015-03-18
| | | | | | | | | | | | ltc_ltc0_lts0_cbc_ctrl1_r() was pointing to broadcast register. Change-Id: I1646f6c68ac944333474029bb78242844424c6f7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428919 Reviewed-by: Matt Craighead <mcraighead@nvidia.com> Tested-by: Matt Craighead <mcraighead@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Wait for CBC op to finish for all LTCsTerje Bergstrom2015-03-18
| | | | | | | | | | | We broadcast CBC operation to all LTCs, but we wait for only one to finish. Bug 1507804 Change-Id: Ib10aa5fe3a34b31862b2d5162c77441f7444a7ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428123
* gpu: nvgpu: Boot FECS to secure modeTerje Bergstrom2015-03-18
| | | | | | | | | | Boot FECS to secure mode if ACR is enabled. Bug 200006956 Change-Id: Ifc107704a6456af837b7f6c513c04d152b2f4d3a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424251
* gpu: nvgpu: Separate PMU firmware load from initTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Separate the code to load PMU firmware from the software init. This allows folding ACR and non-ACR PMU software initialization sequences. Bug 200006956 Change-Id: I74b289747852167e8ebf1be63036c790ae634da4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add timeout to L2 flushAlex Waterman2015-03-18
| | | | | | | | | | | | Add a timeout mechanism to the L2 flushing code for gm20b. Previously the code could spin forever in a loop if some issue were to occur with the L2 causing the flush to fail. Change-Id: I742c7671bac92aeb8e9674c43d30c45b2de4a836 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/423842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove extra g field in pmu_gk20aTerje Bergstrom2015-03-18
| | | | | | | | | | | pmu_gk20a has a pointer to struct gk20a *. As pmu_gk20a is part of gk20a, there's no need to have the circular dependency. Bug 200006956 Change-Id: I6d5d10a93b2fba4a26a1e28b3c5206506dc6cc04 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/424767
* nvgpu: Host side changes to support HS modeSupriya2015-03-18
| | | | | | | | | | | | | | | | | | | GM20B changes in PMU boot sequence to support booting in HS mode and LS mode Bug 1509680 Change-Id: I2832eda0efe17dd5e3a8f11dd06e7d4da267be70 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/423140 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: support non-secure bootSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | | | For non-secure FALCON boot support, by-pass MMU check. Bug 1524197 Change-Id: I735c10a1ea50357c1ea2d5514c73477e76db7e77 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/424005 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement L2 flush in fifo recoveryAlex Waterman2015-03-18
| | | | | | | | | | | | | Implement a full L2 flush (clean and invalidate) for gm20b in the fifo recovery path. Bug 1512176 Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416435 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add cache management registersAlex Waterman2015-03-18
| | | | | | | | | | | | | Add the necessary cache management registers for doing a full L2 flush in GM20b. Bug 1512176 Change-Id: I7799e5e584238a0af02abbf4f49917d7590d97dc Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/417260 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reload ZBC values on rail gate exitTerje Bergstrom2015-03-18
| | | | | | | | | | | When exiting rail gate, we reloaded default ZBC values. The correct behavior is to reload the values. Bug 1447255 Change-Id: I7aad3586dda91a91a3629062a27001af281b955e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418346
* gpu: nvgpu: gm20b: fix compression sharingKevin Huang2015-03-18
| | | | | | | | | | | | | | | | For GM20B alone, the LTC count is already accounted for the HW logic for the CBC base calculation from the postDivide address. So SW doesn't have to explicity divide it by the LTC count in the postDivide address calculation. Bug 1477079 Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/414264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: select NETA for gm20bSeshendra Gadagottu2015-03-18
| | | | | | | | | | Bug 1514021 Change-Id: I5bf942245a42881a418eb9e18c148287b6901ca0 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/415531 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: add support to Maxwell sparse textureKevin Huang2015-03-18
| | | | | | | Bug 1442531 Change-Id: Ie927cca905b2ea9811417e7a1fdfdf9d48f015e2 Signed-off-by: Kevin Huang <kevinh@nvidia.com>
* gpu: nvgpu: Implement ELPG flush for gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | ELPG flush is initiated from a common broadcast register, but must be waited on via per-L2 registers. Split gk20a and gm20b versions of the flush. Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/401545 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Add gm20b fecs/gpccs bootloader supportTerje Bergstrom2015-03-18
| | | | | | | | | Add support for booting FECS and GPCCS via faster bootloader method. We leave this disabled until the bootloader binaries are checked in. Change-Id: I39df5d116f7a33486407518c743638b01923970d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/413005
* gpu: nvgpu: gm20b: add ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: Ic58e21f4d995cf4f4fc7bb5fc6ec84a6c4d25d46 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403214 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add support for SMSKED kindTerje Bergstrom2015-03-18
| | | | | | | | | | | Bug 1470957 Change-Id: Ief7c8970dafcc386a3a954593d4bb3a53be1b2a0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/404261 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Chris Dragan <kdragan@nvidia.com> Tested-by: Chris Dragan <kdragan@nvidia.com>
* gpu: nvgpu: gm20b: Alloc phys mem for CBC in simArto Merilainen2015-03-18
| | | | | | | | | | | | | | | CBC frontdoor access works incorrectly in the simulator if CBC is allocated from IOVA. This patch makes CBC allocation to happen from physical memory if are running in simulator. Bug 1409151 Change-Id: Ide08f4eab6911adc5737001c6d751ee227fec8f9 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/401544 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement gm20b fifo recoveryTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Implement gm20b version of fifo recovery. Bug 1495967 Change-Id: I2792b217178d157427f49e0c450d4ac620399962 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/394138 Reviewed-on: http://git-master/r/401402 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: gm20b: Add fuse headerTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I85038d320ed224074eca14c32d7cb6fd3ed79070 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/401500 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gk20a, gm20b headersKen Adams2015-03-18
| | | | | | | | update headers from latest gen_register/ip_check info Change-Id: Iae892ab7138e7bba4abc821b9d7893e768647daa Signed-off-by: Ken Adams <kadams@nvidia.com> Reviewed-on: http://git-master/r/399382
* gnu: nvgpu: gm20b: CBC clean and invalidateBo Yan2015-03-18
| | | | | | | | | the CBC clean and invalidate is done for gk20a for bug 1409151, now it's time to do the same fo gm20b. the text of this change is strictly copied from gk20a, simply to make build pass. Change-Id: Id717cb1e2ca0fa3f8483c3fd40d7629a9cc85ec9 Signed-off-by: Bo Yan <byan@nvidia.com>
* video: tegra: host: select NETC for gm20bKevin Huang2015-03-18
| | | | | | | | | | | Change-Id: I6e7b5e77907033c7e7cbcc32cae200d46a3700ea Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/387381 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/397712 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
* video: tegra: host: add gm20b channel opKevin Huang2015-03-18
| | | | | | | | | | | | | | Bug 1450792 Change-Id: I09f7c727a773178613fe555eb025ac324da0008e Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/381128 Reviewed-on: http://git-master/r/396373 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Add GPU driver for GM20BBo Yan2015-03-18
this moves GM20B driver to the new location Change-Id: I5fde14e114a8db79738a4c61849912b1ae225fb5
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-12 15:06:41 -0400