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path: root/drivers/gpu/nvgpu/gm20b
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* gpu: nvgpu: Fixes in dupe freeSupriya2015-03-18
| | | | | | | | | | | | | gr_gk20a.c : railgating path the crash was seen with multiple frees happening acr_gm20b.c : failure path, kernel panic was seen, with multiple frees Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494161 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Support for falctraceSupriya2015-03-18
| | | | | | | | | | | | Adding support for falc_trace for ACR Change-Id: Iad638b0de72ff122f43f2250dce6a37adab4cecb Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494162 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpu: nvgpu: Increase GM20b debug monitor cyclesAlex Frid2015-03-18
| | | | | | | | Change-Id: I913b6879e0d1ac89b740c1d088d639cc9b13b9b4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494200 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
* gpu: nvgpu: Add GM20b pll registers error dumpAlex Frid2015-03-18
| | | | | | | | Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Clear PTE ref after freeingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | When clearing sparse buffers, pte->ref must be cleared once the PTE is freed. Bug 1549451 Change-Id: Ie7d3e438ef2c43cbcf893709ae50a67823bf0c9c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494670 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Fix max comptag calculationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix order of calculation for max comptag line calculation. Bug 1549451 Change-Id: I13bf657f0f0b8aafa4d64dacacb74d7224fed379 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494657 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Fix and enable L2 error processingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix L2 error processing to look into interrupts in each L2 and slice. Enable L2 error interrupts. Bug 1549451 Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gm20b: update regops whitelistKevin Huang2015-03-18
| | | | | | | | | | | Bug 1500195 Change-Id: Ie2253f2650844cbc707a3083cc2f6b5150c4a17b Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488508 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | Moved detection of idempotent GPCPLL operations from set_pll_freq() function to its callers, e.g., explicitly check when enable operation is called on already enabled PLL, instead of passing same frequency to set_pll_freq() in such case. Similarly explicitly check when disable operation is called on already disabled PLL. Also moved check for GPU powered on from set_pll_freq() to callers, and skip call to set interface if not. Added last GPCPLL configuration structure updated after successful completion of set_pll_freq() function. Bug 1450787 Change-Id: I8c14b8cab2a8548e98c9b2d223c465c68fb87b61 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: gm20b: dynamically detect priv security for secure boot of falconVijayakumar2015-03-18
| | | | | | | | | | | based on the config setting and fuse secure no non secure boot is done Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/487684 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_slide_gpc_pll()Alex Frid2015-03-18
| | | | | | | | | | | | Passed pll structure to GM20b clk_slide_gpc_pll() function instead of just feedback divider N value. Change-Id: Ic99d23895ae27e48ccd5a12de99a58bab320df16 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488025 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_lock_gpc_pll_under_bypass()Alex Frid2015-03-18
| | | | | | | | | | | | Passed pll structure to GM20b clk_lock_gpc_pll_under_bypass() function instead of individual M/N/PL dividers values. Change-Id: I4881f6fad0e4be63a0eefb7277894d6900e9bb13 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488024 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_program_gpc_pll()Alex Frid2015-03-18
| | | | | | | | | | | | | Passed pll structure to GM20b clk_program_gpc_pll() function instead of enclosing clock structure. Change-Id: I81a3a3c03365f4b6997c17894c5210ebdadcbca6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488023 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Add debugfs access to GM20b GPCPLLAlex Frid2015-03-18
| | | | | | | | | | | Added direct read and write debugfs access to GM20b GPCPLL registers. Change-Id: I203621906ee094991eecd5c18fd5b6c70b20a4c1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/487314 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Disable GM20b idle slow down by defaultAlex Frid2015-03-18
| | | | | | | | Change-Id: I955fe300702f268e5403aab6f47859dd113f92a3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/487301 GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Disable GM20b clock slowdown for monitorAlex Frid2015-03-18
| | | | | | | | | | | Disabled GM20b idle clock slowdown during rate measurements. Change-Id: I20127c1f2816b7a8fe2f208eb21d2decc986d727 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/486324 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Add clock idle slowdown registerAlex Frid2015-03-18
| | | | | | | | | | | | | Added clock idle slowdown register. Fixed duplicated/overlapping therm_peakpower_config8_r and therm_peakpower_config1_r definitions. Change-Id: I37dad714ce5a6730a2f0b7c1b31b509bb1823975 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/486323 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* TEMP: gpu: nvgpu: gm20b: Mask LTC interruptsArto Merilainen2015-03-18
| | | | | | | | | | | LTC interrputs were set to random values at boot. For now, disable all interrupts. Change-Id: Ibb032cac91d3ea9a951fd8c2eb62a783af5bd1a1 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/482639 Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
* gpu: nvgpu: Don't increase GPCPLL rate before bypassAlex Frid2015-03-18
| | | | | | | | | | | | | | | | Do not force GM20b GPCPLL post divider to 1:2 settings before switching to bypass clock if PLL output frequency is increased as a result. Move this step under bypass. However, this step is still needed in case when PLL can be configured without switch to bypass. Bug 1450787 Change-Id: Iab81b0e5a71f44f738a64e15b05df41fdbd61ebe Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/456505 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: gm20b: Fix pm refs in VPR info fetchArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | The code took reference to gk20a by using gk20a_busy_noresume(). This function takes pm runtime reference only to the GPU, however, the code dropped the reference by calling gk20a_idle() which also drops the reference to the platform dependencies (host1x). This patch modifies gm20b_mm_mmu_vpr_info_fetch_wait() to drop only the GPU reference. Change-Id: Ied59381fa302452356768ed59e8ad9af18284e3d Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/482721 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support gk20a virtualizationAingara Paramakuru2015-03-18
| | | | | | | | | | | | | The nvgpu driver now supports using the Tegra graphics virtualization interfaces to support gk20a in a virtualized environment. Bug 1509608 Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/440122 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: manage phys pages at runtimeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Current implementation is based on config GK20A_PHYS_PAGE_TABLES to have APIs to create/free/map/unmap phys pages Remove this config based implementaion and move the APIs so that they are called at runtime based on tegra_platform_is_linsim() In generic APIs, we first check if platform is linsim and if it is then we forward the call to phys page specific APIs Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/488843 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable GM20b GPCPLL SYNC modeAlex Frid2015-03-18
| | | | | | | | | | | | | | Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when powering down GPU. Bug 1450787 Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/456504 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: gm20b: use gpc_mmu to check debug modeKevin Huang2015-03-18
| | | | | | | | | | Bug 1534793 Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/441377 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clear sparse in space freeKevin Huang2015-03-18
| | | | | | | | | | | | | | Gk20a unmaps the addresses binding to dummy page to clear sparse. On Gm20b, we need to free the allocated page table entry for sparse memory. Bug 1538384 Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/448645 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: support TPC floorsweepingKevin Huang2015-03-18
| | | | | | | | | | | Bug 1450798 Change-Id: I371537d086ce1088c6d007676c1fe1e2770dd4e3 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403877 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Comptag size must use LTC countTerje Bergstrom2015-03-18
| | | | | | | | | | | Calculation for comptag backing store must use number of LTCs instead of number of FBPs. Change-Id: If0aa636e09a3d24459987e626fe53bb7c96f1b15 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/453809 Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: remove redundant lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | "isr_enable_lock" was used to protect pmu's isr_enabled flag and pmu enable/disable calls Instead of this extra lock, we can reuse "isr_mutex" for this purpose Bug 200014542 Bug 200014887 Change-Id: Ifbb7d6108effc132266a20517820e470d52a7110 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/453348 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL DVFS fieldsAlex Frid2015-03-18
| | | | | | | | | | | | Added registers/fields definitions for GM20b GPCPLL DVFS support. Bug 1450787 Change-Id: I38b2f84b5cd16661636aca9e284f390b3e25bc91 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/453278 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* nvgpu:Added PROD settings for ELPG sequencingMahantesh Kumbar2015-03-18
| | | | | | | | | Added PROD settings for ELPG sequencing registers Bug 200023161 Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
* arm: tegra: Register tegra-throttle cdev as driverArun Kumar Swain2015-03-18
| | | | | | | | | | | | | | 1. Register tegra-throttle cooling device as a platform driver. 2. Obtain all the platform data (throtlle table info) for all instances of blanced-throtlled cdev from device tree and register them. Change-Id: Ie92685eea3eb5cb18068b195adc9ab5f83762399 Signed-off-by: Arun Kumar Swain <arswain@nvidia.com> Reviewed-on: http://git-master/r/449104 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
* nvgpu: gm20b: Changes for recovery pathSupriya2015-03-18
| | | | | | | | | | | | Bug 200006956 Change-Id: I54b8ead007f8d671bcc731f73377986b880b9082 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/449343 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: select NETB for final NETLISTSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | Final netlist for T210 uses NETB firmware for gpu. Change-Id: Id396f1b6fa53f8d3c7b39ad0f93db230d6ad6d86 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/441355 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Store LTC configurationArto Merilainen2015-03-18
| | | | | | | | | Change-Id: Ia780e6a7cb3579f0d6ed2dca9949a349799535fd Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/448115 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL programming sequenceAlex Frid2015-03-18
| | | | | | | | | | | | | | | | Updated GM20B GPCPLL programming sequence to utilize new glitch-less post divider: - No longer bypass PLL for re-locking if it is already enabled, and post divider as well as feedback divider are changing (input divider change is still under bypass only). - Use post divider instead of external linear divider to introduce (VCO min/2) intermediated step when changing PLL frequency. Bug 1450787 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I4fe60f8eb0d8e59002b641a6bfb29a53467dc8ce
* gpu: nvgpu: Updated GM20b GPCPLL dynamic ramp setupAlex Frid2015-03-18
| | | | | | | | | | | Setup GPCPLL dynamic ramp coefficients based on update rate (instead of hard-coding), since on GM20B high reference clock 38.4MHz allows to use several update rates within supported range. Bug 1450787 Change-Id: I0e14bcb8e3f65cc164fbb66b4adc688fcee9e2d6 Signed-off-by: Alex Frid <afrid@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL locking under bypassAlex Frid2015-03-18
| | | | | | | | | | Moved GPCPLL locking under bypass procedure into separate function. Added SYNC_MODE control during locking. Bug 1450787 Change-Id: I8dbf9427fbdaf55ea20b6876750b518eb738de1b Signed-off-by: Alex Frid <afrid@nvidia.com>
* gpu: nvgpu: gm20b: update gpu headersSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Keep gm20b headers upto date with script output Change-Id: I0916df7c43616b1d9231436a512290c2fa901d64 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/447725 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL parametersAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Updated GPCPLL parameters according to GM20b specification. Modified PLL programming, since on GM20b PLL post divider value is equal to divider setting (which was not the case on GK20a this code was inherited from). Bug 1450787 Change-Id: Ia455ac49040047a3dbcd5d5211f2fbc71dc332ae Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447751 GVS: Gerrit_Virtual_Submit Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL initial configurationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | - Set initial output rate to 1/3 of VCO minimum. - Cleared global BYPASSCTRL to get ready for enabling PLL (this won't bring PLL out of bypass, since SEL_VCO register is cleared). - Added debugfs nodes for BYPASSCTRL and SEL_VCO state. Bug 1450787 Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447750 GVS: Gerrit_Virtual_Submit Reviewed-by: Hoang Pham <hopham@nvidia.com> Tested-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Expand GM20b PLL fields headerAlex Frid2015-03-18
| | | | | | | | | | | | | | | Added masks for GM20b GPCPLL input and post dividers. Bug 1450787 Change-Id: I39a9c7ffb740fa9ef3a614deb2591412e34ef263 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/447857 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* nvgpu: new gpmu ucode compatibilitySupriya2015-03-18
| | | | | | | | | | | | | | For LS PMU new ucode needs to be used. Ucode has interface header file changes too. This patch also has fixes for pmu dmem copy failure Bug 1509680 Change-Id: I8c7018f889a82104dea590751e650e53e5524a54 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/441734 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Make clock operations staticAlex Frid2015-03-18
| | | | | | | | | | | | | Made GK20A and GM20B clock operations static, since they are invoked only via HAL interfaces. Bug 1450787 Change-Id: Ia30218ad4244bd8790b5ef96d1963678d0ba39e1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/441710 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Switch to use GM20B hw header filesHoang Pham2015-03-18
| | | | | | | | | | | Bug 1450787 Change-Id: Id28bd49eadae7b2310410c1676d73b37f57d1443 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/441543 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Fork GM20B clock from GK20A clockHoang Pham2015-03-18
| | | | | | | | | Bug 1450787 Change-Id: Id7fb699d9129a272286d6bc93e0e95844440a628 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/440536 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add gm20b h/w definitionsAlex Frid2015-03-18
| | | | | | | | | | | | | Added SYNC_MODE field, and BYPASSCTRL register; expanded GPC2CLK_OUT_VCODIV field. Bug 1450787 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: Ibf2119a88b0d5f099199920e70b2e88f04b8863b Reviewed-on: http://git-master/r/440928 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: Split clk_ops for GK20A and GM20BHoang Pham2015-03-18
| | | | | | | | | | | Split clk_ops for GK20A and GM20B into different files Bug 1450787 Change-Id: I34d16c54ac40c70854e80588475434c9e50b51a5 Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: http://git-master/r/437771 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gm20b: fix CBC clearWei Sun2015-03-18
| | | | | | | | | | | | | | | gm20b_ltc_cbc_ctrl sent the wrong register value to clear the CBC. Bug 1507804 Change-Id: Ib0d867a122466e50cb15fef3b320fb2ee8455ef2 Signed-off-by: Wei Sun <wsun@nvidia.com> Reviewed-on: http://git-master/r/435297 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Exclude non-secure boot with CONFIG_TEGRA_ACRSeshendra Gadagottu2015-03-18
| | | | | | | | | | | Do not compile non-secure boot code if CONFIG_TEGRA_ACR is defined. Bug 1524197 Change-Id: Id1ec222e00e2229e1d28e406e4ddad99e368296e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/433356 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-22 10:29:36 -0400