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path: root/drivers/gpu/nvgpu/gm20b
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* gpu: nvgpu: Change GPCPLL NA rate in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL frequency change in NA mode outside of bypass. In this case the respective PLL DVFS detection settings are updated in flight. The implemented algorithm relies on characterization providing two frequency limits at the same voltage: max frequency on the F/V curve (Fmax@V) in NA mode with characterized DVFS coefficient, and safe frequency under the curve when DVFS coefficient is zero (Fsafe@V, which is effectively the same as Fmax@V in legacy/non-DVFS mode). Transition between two Fmax@V points on the curve includes: - Lowering frequency to Fsafe@V for the minimum V of the transition end-points - Setting DVFS coefficient to zero - Changing DVFS calibration point to the new voltage - Setting DVFS coefficient characterized for the new voltage - Setting final target frequency Note that voltage is changed by Tegra SoC DVFS before (when voltage increases), or after (whet voltage decreases) the above procedure. This commit kept NA mode disabled. Bug 1555318 Change-Id: Ib5620aaa113dc1caa69ecd402d9c6f68e39c472c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/501042 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Support GPCPLL dynamic ramp in NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL dynamic ramp in NA mode that requires ramping of both integer NDIV and fractional SDM_DIN controls. If NA mode is enabled, dynamic ramp is used only for transition to / from disabled state. PLL frequency in NA mode is still changed under bypass only. This commit kept NA mode disabled. Bug 1555318 Change-Id: I91f5722a485d1b66b6113aa9c35a2fe36c38ea80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/500637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL NA mode basic supportAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this mode PLL internal DVFS mechanism is engaged, and output frequency is scaled with voltage automatically. The scaling coefficients in this commit are preliminary, pending characterization. If NA mode is enabled, any frequency change is done under PLL bypass, with no dynamic ramp allowed. This commit kept NA mode disabled. Bug 1555318 Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499488 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Support 512 channels in gm20bTerje Bergstrom2015-03-18
| | | | | | | | | Retrieve channel count from gm20b specific header instead of the gk20a header. This increases channel count from 128 to 512. Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/500623
* gpu: nvgpu: gm20b: Fix build warningsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add GM20B GPCPLL h/w definitionsAlex Frid2015-03-18
| | | | | | | | | | | | | Expanded GM20B GPCPLL definitions of DVFS registers. Bug 1450787 Change-Id: I51d049be70badfedd8c451019b10770b4fb31e80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499487 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: add API to recover TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - add and export API "gk20a_fifo_recover_tsg()" to recover a TSG - if TSG is running on any engine, then trigger MMU fault on those engines - otherwise, abort each channel in TSG - modify channel specific API engines_on_ch() to generic engines_on_id() which will take an ID and a flag to specify whether ID is for channel or TSG and return engines running on that ID - modify channel specific API get_faulty_channel() to generic get_faulty_id_type() which will take pointers to ID and type of ID (either a regular channel or TSG) - remove runlist update from recover_ch() since no need to touch runlist during recovery - set error notifier first and then only abort the channels for TSG recovery path - also, add necessary accessors to get engine status type as TSG Bug 1470692 Change-Id: I7137f611f80916b3d256d4b0dc6e5cf1e93eef6f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/497873 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Change GM20B post-divider in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | Restored changing GM20B GPCPLL post-divider in flight with the following limitation: post divider transition is glitch-less only if there is common "1" in binary representation of old and new settings. Transitions that may create glitch are implemented in glitch-less steps with minimum possible interim divider value (for example, 1 <=> 2 transition has interim value 3: 1 <=> 3 <=> 2). Steps allowed for glitch-less transitions may not always have frequency jump at/below VCO min/2 (in the example above 1st step jumps 2/3 of VCOmin). Enabled external linear divider at 1:2 during such steps. Used extra write of the same data when changing GM20b linear divider. Bug 1552225 Change-Id: Ie8fba2fbe44afd34ca68f5f355bd302b7426a632 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/496319 (cherry picked from commit bdd21e0003032fe664bd20f163dbab9942fd1d1d) Reviewed-on: http://git-master/r/499193 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL bypass operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | - Skipped PLL re-locking if only post-divider is changing under bypass - Added 1us delay after switch to bypass clock source - Changed wait for lock under bypass resolution from 2us to 1us Change-Id: I259581c00c417752263ef3b2ea057200bb78ecbf Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495473 (cherry picked from commit d90a19b8bf59c608a2a3a891b34ca714dfe990e9) Reviewed-on: http://git-master/r/499192 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Disable illegal compstat access intrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Disable illegal compstat access interrupt. We access compstat backing store to handle CDE swizzling. Also change the magic number for evicted_cb to use a generated value. Change-Id: I79b299abbffcb90497690ba4fc55d8517a3dbd87 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/496444 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com>
* gpu: nvgpu: gm20b: disable slcg fbSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | copy disable values in slcg fb to the prod column to avoid hang issues with SLCG enable. Bug 1550628 Change-Id: I941c6e625cda41bca8805033b5b2a0387eed4ab5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/496122 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add API to preempt TSGDeepak Nibade2015-03-18
| | | | | | | | | | | | | | Add API gk20a_fifo_preempt_tsg() which takes ID of tsg and preempts it Bug 1514064 Bug 1470692 Change-Id: I1d52c1dd7a9aecc1314b0f223fe4eedecc033629 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/495583 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Use pgsz_idx instead of page_sizeTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Alloc space writes the page size to a field that requires pgsz_idx. That can cause corruption in internal kernel structures. Clear_sparse treated a parameter as page size instead of index. Bug 1549451 Change-Id: I73ce17b99aae6865056facce72d2ab9ca8b3f81d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/495692
* gpu: nvgpu: Bypass for GM20B post-divider changeAlex Frid2015-03-18
| | | | | | | | | | | Switch GM20b GPCPLL under bypass when changing post-divider setting (for now, don't assume that post-divider is glitch-less). Change-Id: I62b1285c035de0913207a86c41f37b7765da3893 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/495300 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Fixes in dupe freeSupriya2015-03-18
| | | | | | | | | | | | | gr_gk20a.c : railgating path the crash was seen with multiple frees happening acr_gm20b.c : failure path, kernel panic was seen, with multiple frees Change-Id: Ifc5e78c0ee74799c7f78e6030c02d1a27d545a1e Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494161 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Support for falctraceSupriya2015-03-18
| | | | | | | | | | | | Adding support for falc_trace for ACR Change-Id: Iad638b0de72ff122f43f2250dce6a37adab4cecb Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/494162 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Regenerate clock gating listsTerje Bergstrom2015-03-18
| | | | | | | | | | Regenerate clock gating lists. Add new blocks, and takes them into use. Also moves some clock gating settings to be applied at the earliest possible moment right after reset. Change-Id: I21888186c200f7a477c63bd3332e8ed578f63741 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/457698
* gpu: nvgpu: Increase GM20b debug monitor cyclesAlex Frid2015-03-18
| | | | | | | | Change-Id: I913b6879e0d1ac89b740c1d088d639cc9b13b9b4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494200 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
* gpu: nvgpu: Add GM20b pll registers error dumpAlex Frid2015-03-18
| | | | | | | | Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/494164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Clear PTE ref after freeingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | When clearing sparse buffers, pte->ref must be cleared once the PTE is freed. Bug 1549451 Change-Id: Ie7d3e438ef2c43cbcf893709ae50a67823bf0c9c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494670 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: Fix max comptag calculationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix order of calculation for max comptag line calculation. Bug 1549451 Change-Id: I13bf657f0f0b8aafa4d64dacacb74d7224fed379 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494657 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Fix and enable L2 error processingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix L2 error processing to look into interrupts in each L2 and slice. Enable L2 error interrupts. Bug 1549451 Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* gpu: nvgpu: gm20b: update regops whitelistKevin Huang2015-03-18
| | | | | | | | | | | Bug 1500195 Change-Id: Ie2253f2650844cbc707a3083cc2f6b5150c4a17b Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/488508 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL operationsAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | Moved detection of idempotent GPCPLL operations from set_pll_freq() function to its callers, e.g., explicitly check when enable operation is called on already enabled PLL, instead of passing same frequency to set_pll_freq() in such case. Similarly explicitly check when disable operation is called on already disabled PLL. Also moved check for GPU powered on from set_pll_freq() to callers, and skip call to set interface if not. Added last GPCPLL configuration structure updated after successful completion of set_pll_freq() function. Bug 1450787 Change-Id: I8c14b8cab2a8548e98c9b2d223c465c68fb87b61 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488027 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: gm20b: dynamically detect priv security for secure boot of falconVijayakumar2015-03-18
| | | | | | | | | | | based on the config setting and fuse secure no non secure boot is done Change-Id: I5937ba945c5a3a86f72e0f2a9078fcde01977137 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/487684 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_slide_gpc_pll()Alex Frid2015-03-18
| | | | | | | | | | | | Passed pll structure to GM20b clk_slide_gpc_pll() function instead of just feedback divider N value. Change-Id: Ic99d23895ae27e48ccd5a12de99a58bab320df16 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488025 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_lock_gpc_pll_under_bypass()Alex Frid2015-03-18
| | | | | | | | | | | | Passed pll structure to GM20b clk_lock_gpc_pll_under_bypass() function instead of individual M/N/PL dividers values. Change-Id: I4881f6fad0e4be63a0eefb7277894d6900e9bb13 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488024 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Re-factor GM20b clk_program_gpc_pll()Alex Frid2015-03-18
| | | | | | | | | | | | | Passed pll structure to GM20b clk_program_gpc_pll() function instead of enclosing clock structure. Change-Id: I81a3a3c03365f4b6997c17894c5210ebdadcbca6 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/488023 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Add debugfs access to GM20b GPCPLLAlex Frid2015-03-18
| | | | | | | | | | | Added direct read and write debugfs access to GM20b GPCPLL registers. Change-Id: I203621906ee094991eecd5c18fd5b6c70b20a4c1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/487314 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Disable GM20b idle slow down by defaultAlex Frid2015-03-18
| | | | | | | | Change-Id: I955fe300702f268e5403aab6f47859dd113f92a3 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/487301 GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Disable GM20b clock slowdown for monitorAlex Frid2015-03-18
| | | | | | | | | | | Disabled GM20b idle clock slowdown during rate measurements. Change-Id: I20127c1f2816b7a8fe2f208eb21d2decc986d727 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/486324 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: Add clock idle slowdown registerAlex Frid2015-03-18
| | | | | | | | | | | | | Added clock idle slowdown register. Fixed duplicated/overlapping therm_peakpower_config8_r and therm_peakpower_config1_r definitions. Change-Id: I37dad714ce5a6730a2f0b7c1b31b509bb1823975 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/486323 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* TEMP: gpu: nvgpu: gm20b: Mask LTC interruptsArto Merilainen2015-03-18
| | | | | | | | | | | LTC interrputs were set to random values at boot. For now, disable all interrupts. Change-Id: Ibb032cac91d3ea9a951fd8c2eb62a783af5bd1a1 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/482639 Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
* gpu: nvgpu: Don't increase GPCPLL rate before bypassAlex Frid2015-03-18
| | | | | | | | | | | | | | | | Do not force GM20b GPCPLL post divider to 1:2 settings before switching to bypass clock if PLL output frequency is increased as a result. Move this step under bypass. However, this step is still needed in case when PLL can be configured without switch to bypass. Bug 1450787 Change-Id: Iab81b0e5a71f44f738a64e15b05df41fdbd61ebe Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/456505 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
* gpu: nvgpu: gm20b: Fix pm refs in VPR info fetchArto Merilainen2015-03-18
| | | | | | | | | | | | | | | | | The code took reference to gk20a by using gk20a_busy_noresume(). This function takes pm runtime reference only to the GPU, however, the code dropped the reference by calling gk20a_idle() which also drops the reference to the platform dependencies (host1x). This patch modifies gm20b_mm_mmu_vpr_info_fetch_wait() to drop only the GPU reference. Change-Id: Ied59381fa302452356768ed59e8ad9af18284e3d Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/482721 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: support gk20a virtualizationAingara Paramakuru2015-03-18
| | | | | | | | | | | | | The nvgpu driver now supports using the Tegra graphics virtualization interfaces to support gk20a in a virtualized environment. Bug 1509608 Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676 Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com> Reviewed-on: http://git-master/r/440122 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: manage phys pages at runtimeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Current implementation is based on config GK20A_PHYS_PAGE_TABLES to have APIs to create/free/map/unmap phys pages Remove this config based implementaion and move the APIs so that they are called at runtime based on tegra_platform_is_linsim() In generic APIs, we first check if platform is linsim and if it is then we forward the call to phys page specific APIs Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/488843 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Disable GM20b GPCPLL SYNC modeAlex Frid2015-03-18
| | | | | | | | | | | | | | Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when powering down GPU. Bug 1450787 Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/456504 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: gm20b: use gpc_mmu to check debug modeKevin Huang2015-03-18
| | | | | | | | | | Bug 1534793 Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/441377 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: clear sparse in space freeKevin Huang2015-03-18
| | | | | | | | | | | | | | Gk20a unmaps the addresses binding to dummy page to clear sparse. On Gm20b, we need to free the allocated page table entry for sparse memory. Bug 1538384 Change-Id: Ie2409ab016c29f42c5f7d97dd7287b093b47f9df Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/448645 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: support TPC floorsweepingKevin Huang2015-03-18
| | | | | | | | | | | Bug 1450798 Change-Id: I371537d086ce1088c6d007676c1fe1e2770dd4e3 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403877 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Comptag size must use LTC countTerje Bergstrom2015-03-18
| | | | | | | | | | | Calculation for comptag backing store must use number of LTCs instead of number of FBPs. Change-Id: If0aa636e09a3d24459987e626fe53bb7c96f1b15 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/453809 Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: remove redundant lockDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | "isr_enable_lock" was used to protect pmu's isr_enabled flag and pmu enable/disable calls Instead of this extra lock, we can reuse "isr_mutex" for this purpose Bug 200014542 Bug 200014887 Change-Id: Ifbb7d6108effc132266a20517820e470d52a7110 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/453348 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL DVFS fieldsAlex Frid2015-03-18
| | | | | | | | | | | | Added registers/fields definitions for GM20b GPCPLL DVFS support. Bug 1450787 Change-Id: I38b2f84b5cd16661636aca9e284f390b3e25bc91 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/453278 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* nvgpu:Added PROD settings for ELPG sequencingMahantesh Kumbar2015-03-18
| | | | | | | | | Added PROD settings for ELPG sequencing registers Bug 200023161 Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
* arm: tegra: Register tegra-throttle cdev as driverArun Kumar Swain2015-03-18
| | | | | | | | | | | | | | 1. Register tegra-throttle cooling device as a platform driver. 2. Obtain all the platform data (throtlle table info) for all instances of blanced-throtlled cdev from device tree and register them. Change-Id: Ie92685eea3eb5cb18068b195adc9ab5f83762399 Signed-off-by: Arun Kumar Swain <arswain@nvidia.com> Reviewed-on: http://git-master/r/449104 Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
* nvgpu: gm20b: Changes for recovery pathSupriya2015-03-18
| | | | | | | | | | | | Bug 200006956 Change-Id: I54b8ead007f8d671bcc731f73377986b880b9082 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/449343 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: select NETB for final NETLISTSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | Final netlist for T210 uses NETB firmware for gpu. Change-Id: Id396f1b6fa53f8d3c7b39ad0f93db230d6ad6d86 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/441355 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Store LTC configurationArto Merilainen2015-03-18
| | | | | | | | | Change-Id: Ia780e6a7cb3579f0d6ed2dca9949a349799535fd Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/448115 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Update GM20B GPCPLL programming sequenceAlex Frid2015-03-18
| | | | | | | | | | | | | | | | Updated GM20B GPCPLL programming sequence to utilize new glitch-less post divider: - No longer bypass PLL for re-locking if it is already enabled, and post divider as well as feedback divider are changing (input divider change is still under bypass only). - Use post divider instead of external linear divider to introduce (VCO min/2) intermediated step when changing PLL frequency. Bug 1450787 Signed-off-by: Alex Frid <afrid@nvidia.com> Change-Id: I4fe60f8eb0d8e59002b641a6bfb29a53467dc8ce
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-12 16:58:36 -0400