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path: root/drivers/gpu/nvgpu/gm20b
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* gpu: nvgpu: Submit coverity fixesTerje Bergstrom2015-03-18
| | | | | | | | | | Clear ioctl buffer and fix double free, and error case memory leak. Bug 200059216 Change-Id: I21cc2b0f6a7e8fca09f72caf4c54d570b13f400b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/655347
* gpu:nvgpu:gm20b: update pg sequencer dataVijayakumar2015-03-18
| | | | | | | | | | | | | | bug 1553301 sequencer data picked up from p4sw #19041893 Change-Id: I3d05972201572e3db31d1b46e93c03dda3e58d54 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/657023 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Export gm20b kind functionsTerje Bergstrom2015-03-18
| | | | | | | | | Bug 1567274 Change-Id: I21dadc0e473f174e7ae876b934dcd938bc956453 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/607007 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Implement per-chip pagepool sizeTerje Bergstrom2015-03-18
| | | | | | | | | | Bug 1567274 Change-Id: Ib366f56c109f60be98435124e9e73697d161c4d0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606935 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Use driver-wide timeout for ACR bootTerje Bergstrom2015-03-18
| | | | | | | | | | | In simulation we disable timeouts system-wide. Use the system-wide timeout for ACR boot to enable ACR boot in simulation. Bug 1546850 Change-Id: I58fc0485725195feab24ae5fe4f249116668bbcc Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/606273
* gpu: nvgpu: Physical page bits to be per chipTerje Bergstrom2015-03-18
| | | | | | | | | | Retrieve number of physical page bits based on chip. Bug 1567274 Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601700
* dvfs: tegra21: Rename predict interfacesAlex Frid2015-03-18
| | | | | | | | | | | Renamed predict voltage interfaces to clarify temperature dependencies accounted for each interface. Change-Id: Ic76b25a6a8b22f9268d4b3e4186c53b6c3461192 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/562194 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add HAL for add ZBC color & depthTerje Bergstrom2015-03-18
| | | | | | | | | | | Turn add ZBC functions into HALs that can be filled per chip. Bug 1567274 Change-Id: Ic6ef29d3353d4a0079ea0c80f513ffd579fe554f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601109 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: Per-alloc alignmentTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I8b7e86afb68adf6dd33b05995d0978f42d57e7b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554185 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Retrieve intr & reset id from HWTerje Bergstrom2015-03-18
| | | | | | | | | | | | Query interrupt number and reset id from HW. Use the number from HW when enabling and detecting interrupts. Bug 200036089 Bug 1567274 Change-Id: If9cb4db79a19dcb193ba7ad9db7081f4fe1ab433 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/600988
* gpu: nvgpu: fix gm20b floorsweep APIDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | Rewrite gr_gm20b_ctx_state_floorsweep() to include necessary register writes for gm20b tpc floorsweeping. This includes : - update the loop to write gr_gpc0_tpc0_sm_cfg_r() and gr_gpc0_gpm_pd_sm_id_r() - for gr_pd_num_tpc_per_gpc_r(i), we just need to write register with i = 0 and the value being written is tpc count in that gpc - gr_fe_tpc_fs_r() needs to have logical list of TPCs after floorsweeping. Get this value from pes_tpc_mask. - gr_cwd_gpc_tpc_id_tpc0_f() and gr_cwd_sm_id_tpc0_f() also refer to logical ids and hence no need to check tpc_fs_mask to configure these registers Bug 1513685 Change-Id: I82dc36a223fbd21e814e58e4d67738d7c63f04a7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/601117 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: support config of TPC FUSE dynamicallyDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Follow steps below to config active TPC number: echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle where, 0x1 : disable TPC1 0x2 : disable TPC0 0x3 : both TPCs active Also, add API set_gpc_tpc_mask to update the TPCs and call this API after update to sysfs "tpc_fs_mask" Once fuses are updated for new TPC settings, we need to reconfigure GR and golden_image. Hence disable gr->sw_ready and golden_image_initialized flags. Also, initialize gr->tpc_count = 0 each time in gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count Bug 1513685 Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/552606 Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Add GPCPLL DVFS state to debug printsAlex Frid2015-03-18
| | | | | | | | | Bug 1555318 Change-Id: I80655e047963619b5a3d7e9155db13c9396417fe Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/598970 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* dvfs: tegra21: Don't allow NA mode on certain partsAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | GM20b GPCPLL NA mode should not be enabled on Tegra21 parts with speedo revision 0 or 1, even when CONFIG_TEGRA_USE_NA_GPCPLL is set. Respectively, in this case non-NA GPU DVFS table must be selected. To accommodate this restriction added GPU speedo id 1, and mapped parts with revision 2 and above to this new speedo id. Kept speedo id 0 for parts with revision 0 or 1. Only non-NA DVFS table is selected for speedo id 0. Either non-NA or NA mode DVFS table can be selected by CONFIG_TEGRA_USE_NA_GPCPLL setting for parts with speedo id 1. GM20b GPCPLL mode selection procedure is updated accordingly, so that NA mode is disabled for speedo id 0, and selected for speedo id 1 by CONFIG_TEGRA_USE_NA_GPCPLL. The latter takes precedence over GPCPLL ADC calibration fuses - if config option is set, and part has speedo id 1, NA mode is enabled even if calibration fuses are not burnt (less accurate s/w self-calibration is used in this case). Bug 1555318 Change-Id: I3948cb945206d0bc0f9f2bb6da5505c50ffc2af1 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/594718 Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: GPU characteristics additionsSami Kiminki2015-03-18
| | | | | | | | | | | | | | | | | Add the following info into GPU characteristics: available big page sizes, support indicators for sync fence fds and cycle stats, gpc mask, SM version, SM SPA version and warp count, and IOCTL interface levels. Also, add new IOCTL to fetch TPC masks. Bug 1551769 Bug 1558186 Change-Id: I8a47d882645f29c7bf0c8f74334ebf47240e41de Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: http://git-master/r/562904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add class numbers to characteristicsTerje Bergstrom2015-03-18
| | | | | | | | | | | Some kernel APIs rely on user space knowing class numbers. Allow querying the numbers from kernel. Bug 1567274 Change-Id: Idec2fe8ee983ee74bcbf9dfc98f71bbcc1492cfb Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/594402
* gpu: nvgpu: Add GPCPLL parameters to GM20b debugfsAlex Frid2015-03-18
| | | | | | | | | Bug 1555318 Change-Id: I0338e5d46c7f7d910faada0205dccf28aa62d6c2 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/594746 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gm20b: remove duplicate regops whitelistSeshendra Gadagottu2015-03-18
| | | | | | | | | | | | | | Manually removed duplicate entries in regops whitelist. Once RM tools is available, then whitelist update will happen through script. Bug 1500195 Change-Id: I913c48365e43febcd350a9bfc73d42a27f24e2f7 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/592972 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: Regenerate HW headersTerje Bergstrom2015-03-18
| | | | | | | Regenerate HW headers after adding SM debugger registers. Change-Id: Icc47c11f8e9ff52c0cf1f3a54233fb781c2c2b67 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: halify tpc lookupMayank Kaushik2015-03-18
| | | | | | | | | | | | Since the number of TPCs is different between GM20B and GK20a, the function to look up the number of TPCs needs to be halified. Change-Id: I19dab9a7105814f86c08c92283a0bb70abb6aa00 Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/500064 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create a hal function for smpc warMayank Kaushik2015-03-18
| | | | | | | | | | | Create a HAL function for applying the SMPC workaround.The workaround is only needed on gk20a, and not on gm20b. Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com> Reviewed-on: http://git-master/r/539187 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Per-chip interrupt processingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Move accesses to MC registers under HAL so that they can be reimplemented per chip. Do chip detection and HAL initialization only once. Bug 1567274 Change-Id: I20bf2f439d267d284bfd536f1a1dfb5d5a2dce4c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590385
* gpu: nvgpu: Changes to support LS sigSupriya2015-03-18
| | | | | | | | | | | | Support added to send PMU and FECS signatures to ACR ucode Bug 200046413 Change-Id: Ie1babb640be20a697ad4d6dd18bd11161edb263c Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Supriya <ssharatkumar@nvidia.com> Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
* Revert "gpu: nvgpu: GR and LTC HAL to use const structs"Sam Payne2015-03-18
| | | | | | | | | | | This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e. Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/592221 Tested-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: GR and LTC HAL to use const structsTerje Bergstrom2015-03-18
| | | | | | | | | | | Convert GR and LTC HALs to use const structs, and initialize them with macros. Bug 1567274 Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590371
* gpu: nvgpu: gm20b: Support secure FECS recoveryVijayakumar2015-03-18
| | | | | | | | | | | | | When falcons are secured use PMU commands to reload FECS firmware. Bug 200042729 Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552544 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Sync gk20a and gm20b headersTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Split L2 size calculation per chipTerje Bergstrom2015-03-18
| | | | | | | | | | gk20a and gm20b calculate L2 size with different parameters. Split the function for calculating size so that it does not query GPU id. Bug 1567274 Change-Id: I09510c1bf0286c9df125d74e51df322c32bde646 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix build without Tegra clk frameworkTerje Bergstrom2015-03-18
| | | | | | | | | | | | Do not build clock code if TEGRA_CLK_FRAMEWORK is not defined. Also make GK20A_DEVFREQ depend on TEGRA_CLK_FRAMEWORK, and build scaling governor only if GK20A_DEVFREQ is enabled. Bug 1567274 Change-Id: I6ea1462e7a110fb46c9d66ceda71167cff19699e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/562475
* gpu: nvgpu: select ucode boot init by signatureKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | | | | | Compute a signature checksum for ctxsw ucode boot section and determine the format of boot initialization data by it. This unifies gk20a and gk20b ucode segment loading a lot by separating the bootloader loading logic to separate functions. Note: Whenever the boot segment binary changes, its updated signature must be added here. Management of different bootloaders must be supported for repo-crossing staging issues. Bug 1519397 Change-Id: I96f9b905d3631dfdebf71ea3a652a0968615fd0a Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/556679 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: allow building as a separate moduleKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Include object files of gk20a, gm20b and vgpu in the same composite object nvgpu.o in the top-level makefile, and remove the old makefiles. This helps in building the driver as a separate module. Bug 1476801 Change-Id: I93531c0f1a20e46904a429e492f8ed32e4f0c4a1 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/557971 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Protect GM20b clock init from div-by-0Alex Frid2015-03-18
| | | | | | | | | | | | Protected GM20b clock initialization from div-by-0 in case when safe fmax at Vmin is not known, and the respective interface returns zero. Change-Id: I2064a3182c93f283c7e85c247601203dd1f71af4 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559059 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* dvfs: tegra21: Rename thermal safe maximum frequencyAlex Frid2015-03-18
| | | | | | | | | | Renamed field and function operated on thermal safe maximum frequency to make it clear that it is fmax at Vmin (not global fmax). Change-Id: Ie2b5234e87dc5dc03ccdaeb2916f0b776e56b640 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/559058 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Implement 64k large page supportTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Common VM initializerTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | Merge initialization code from gk20a_init_system_vm(), gk20a_init_bar1_vm() and gk20a_vm_alloc_share() into gk20a_init_vm(). Remove redundant page size data, and move the page size fields to be VM specific. Bug 1558739 Bug 1560370 Change-Id: I4557d9e04d65ccb48fe1f2b116dd1bfa74cae98e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: write gpccs start only onceVijayakumar2015-03-18
| | | | | | | | | | | Writing start bit twice can confuse falcon and results in random behavior. Bug 200040021 Change-Id: I62eb8e4632ac4fc471d931155471084ee0f9d0a4 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu:gm20b: disable irqs when hs pmu executesVijayakumar2015-03-18
| | | | | | | | | | | | | bug 200040021 polling halt irq to check for hs bin completion keep irqs disabled to avoid executing irq handler Change-Id: Ic245d89580444dcbf1cf5ec34bfe0f8b0c5bbc0f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/554659 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Override GM20b RAM SVOP PDP fusesAlex Frid2015-03-18
| | | | | | | | | | | | | | | Override GM20b RAM SVOP PDP fuses with 0x2 setting during clock initialization. Bug 1550997 Change-Id: I9a873b892a2db4af384a9a7af4470562cdcb1572 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499554 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b RAM SVOP PDP fuse registersAlex Frid2015-03-18
| | | | | | | | | | | | Bug 1550997 Change-Id: I25551fdcb9f7d43dc8631305b784aa9c04040139 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499553 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b GPCPLL NA mode settingsAlex Frid2015-03-18
| | | | | | | | | | | | | - Updated DFS_COEFF slope/intercept parameters - Specified VCO control gain - Increased safe DVFS margin to 10% Bug 1555318 Change-Id: I619704b7ba029d77ea1019a86003c3e8d80d04d8 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552446 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change quantize order in GPCPLL NA modeAlex Frid2015-03-18
| | | | | | | | | | | | When calculating fractional divider in GPCPLL NA mode quantize voltage before (used to do it after) applying DFS_COEFF, to follow h/w order. Bug 1555318 Change-Id: I37be2bc73cd1f849695b94acc4ff21caf26e8b97 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552741 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Update GM20b clock initializationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | - Removed unnecessary static "initialized" variable (sw_ready flag is protecting from multiple initializations, anyway). - Used max frequency at min voltage to set initial configuration of GPCPLL in both NA and non-NA mode. For backward compatibility made sure initial PLL output rate do not exceed 1/3 of VCO minimum. Bug 1555318 Change-Id: If970c27442ea1109d4503a322998a6a26159c345 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/552370 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: gm20b: fix dbg msg from secure pmuVijayakumar2015-03-18
| | | | | | | | | | dma params for dbg msgs not passed correctly Change-Id: Ic4ba2bf282b8c339a8c8f6fecd297394fd5771dd Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552073 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: create new nvgpu ioctl headerKonsta Holtta2015-03-18
| | | | | | | | | | | | | | | Move nvgpu ioctls from the many user space interface headers to a new single nvgpu.h header under include/uapi. No new code or replaced names are introduced; this change only moves the definitions and changes include directives accordingly. Bug 1434573 Change-Id: I4d02415148e437a4e3edad221e08785fac377e91 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542651 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: rename gpu ioctls and structs to nvgpuKonsta Holtta2015-03-18
| | | | | | | | | | | | | | To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Prepare for GPCPLL NA data integrationAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | In preparation for GM20B GPCPLL NA data integration: - Added VCO control initialization code (no data, yet) - Replaced absolute safe margin with relative percentage (preliminary 8%) - Retrieved maximum safe frequency at minimum voltage from GPU DVFS table, instead of hard-coded macro (also fix the name of the limit: maximum instead of minimum) - Updated comments Bug 1555318 Change-Id: I49a7a90cc4bc29e181065ebd2cf9d214edae6465 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/542462 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Change GPCPLL NA rate in flightAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL frequency change in NA mode outside of bypass. In this case the respective PLL DVFS detection settings are updated in flight. The implemented algorithm relies on characterization providing two frequency limits at the same voltage: max frequency on the F/V curve (Fmax@V) in NA mode with characterized DVFS coefficient, and safe frequency under the curve when DVFS coefficient is zero (Fsafe@V, which is effectively the same as Fmax@V in legacy/non-DVFS mode). Transition between two Fmax@V points on the curve includes: - Lowering frequency to Fsafe@V for the minimum V of the transition end-points - Setting DVFS coefficient to zero - Changing DVFS calibration point to the new voltage - Setting DVFS coefficient characterized for the new voltage - Setting final target frequency Note that voltage is changed by Tegra SoC DVFS before (when voltage increases), or after (whet voltage decreases) the above procedure. This commit kept NA mode disabled. Bug 1555318 Change-Id: Ib5620aaa113dc1caa69ecd402d9c6f68e39c472c Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/501042 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Support GPCPLL dynamic ramp in NA modeAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | Added support for GM20b GPCPLL dynamic ramp in NA mode that requires ramping of both integer NDIV and fractional SDM_DIN controls. If NA mode is enabled, dynamic ramp is used only for transition to / from disabled state. PLL frequency in NA mode is still changed under bypass only. This commit kept NA mode disabled. Bug 1555318 Change-Id: I91f5722a485d1b66b6113aa9c35a2fe36c38ea80 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/500637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Add GM20b GPCPLL NA mode basic supportAlex Frid2015-03-18
| | | | | | | | | | | | | | | | | | | | Added basic support for GM20b GPCPLL noise-aware(NA) mode. In this mode PLL internal DVFS mechanism is engaged, and output frequency is scaled with voltage automatically. The scaling coefficients in this commit are preliminary, pending characterization. If NA mode is enabled, any frequency change is done under PLL bypass, with no dynamic ramp allowed. This commit kept NA mode disabled. Bug 1555318 Change-Id: I8d96a10006155635797331bae522fb048d3dc4a0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/499488 GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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