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path: root/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
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* gpu: nvgpu: add cg and pg functionDebarshi Dutta2019-05-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new power/clock gating functions that can be called by other units. New clock_gating functions will reside in cg.c under common/power_features/cg unit. New power gating functions will reside in pg.c under common/power_features/pg unit. Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable elpg and also in gr_gk20a_elpg_protected macro to access gr registers. Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled and slcg_enabled thread safe. JIRA NVGPU-2014 Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2025493 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> (cherry-picked from c90585856567a547173a8b207365b3a4a3ccdd57 in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2108406 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: PMU init sequence changeMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: ACR code refactorMahantesh Kumbar2018-09-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change location of gk20a.h#include <nvgpu/gk20a.h>ddutta2018-09-14
| | | | | | | | | | | | | | | | | | | | Update the include location of gk20a.h to include/nvgpu/gk20a.h in the following directories. nvgpu/gm20b/ nvgpu/gp10b/ nvgpu/gv11b/ Jira NVGPU-597 Change-Id: Ie38d4a72bb65c41bd30058350509bfa7e87bb64e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822789 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use debug sig for NVDEC if on dbg SKUTerje Bergstrom2018-08-31
| | | | | | | | | | | | | | Debug fused chips do not have production signature. Use debug signature for memory unlock binary. Requires also exporting a HAL for checking debug mode from PMU. Bug 200445202 Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809225 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HALDebarshi Dutta2018-08-29
| | | | | | | | | | | | | | | | | | | | In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Fix MISRA 15.6 violationsSrirangan2018-08-28
| | | | | | | | | | | | | | | | | | MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I1651ae8ee680bdeb48606569c4e8c2fc7cb87f20 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805077 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Move fuse HAL to commonTerje Bergstrom2018-08-20
| | | | | | | | | | | | Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
* gk20a: nvgpu: Remove io.h dependency from gk20a.hDebarshi Dutta2018-07-30
| | | | | | | | | | | | | | | | In the current code, gk20a.h includes io.h which gets directly included in a lot of other files. io.h contains methods which uses a struct gk20a as a parameter leading to a circular dependency between io.h and gk20a.h. This can be mitigated by removing io.h from gk20a.h as part of larger effort to moving gk20a.h to nvgpu/gk20a.h JIRA NVGPU-597 Change-Id: I93e504fa9371b88152737b342a75580c65e8f712 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1787316 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Remove gk20a_dbg* functionsTerje Bergstrom2018-05-09
| | | | | | | | | | | | | | | Switch all logging to nvgpu_log*(). gk20a_dbg* macros are intentionally left there because of use from other repositories. Because the new functions do not work without a pointer to struct gk20a, and piping it just for logging is excessive, some log messages are deleted. Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704148 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gv11b: Update elpg init seq for gv11b.Deepak Goyal2017-12-08
| | | | | | | | | | | | | | | | This updates register address/value pairs for ELPG init sequence in GV11B. Bug 200365505. Change-Id: I62517c378c39f5025f797cf849f10e6b0eae27a8 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1612642 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Change license for common files to MITTerje Bergstrom2017-09-26
| | | | | | | | | | | | Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I1474065f4b552112786974a16cdf076c5179540e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1565880 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Reorg pmu HAL initializationSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8839ac99e87153637005e23b3013237f57275c54 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530982 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Move non-fp pmu members from gpu_opsSunny He2017-08-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move non-function pointer members out of the pmu and pmu_ver substructs of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to g.pmu_ver_cmd_id_zbc_table_update - g.ops.pmu.lspmuwprinitdone has been changed to g.pmu_lsf_pmu_wpr_init_done - g.ops.pmu.lsfloadedfalconid has been changed to g.pmu_lsf_loaded_falcon_id Boolean flags have been implemented using the enabled.h API - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to common flag NVGPU_PMU_ZBC_SAVE - g.ops.pmu.fecsbootstrapdone moved to common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE Jira NVGPU-74 Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530981 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add struct gk20a ptr to FUSE APIsAlex Waterman2017-08-14
| | | | | | | | | | | | | | | | | | | Add a pointer to struct gk20a to the FUSE APIs. This helps QNX builds avoid any static data definitions. Also this change plumbs struct gk20a in some of the Linux clk code and fixes a few minor style nits. Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1537611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Remove privsecurity flag from gpu_opsSunny He2017-07-26
| | | | | | | | | | | | | | | | | Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: use u32 for timeout API durationKonsta Holtta2017-07-07
| | | | | | | | | | | | | | | | A negative value in the timeout duration does not have any special uses, so change the duration type to u32 (from just int). Delete some unnecessary typecasts to int. Also change MAX_SCHEDULE_TIMEOUT to ULONG_MAX in default gr idle timeout because the value is in milliseconds instead of scheduling units and to drop unnecessary Linux dependency. Change-Id: I5cf6febd4f1cb00c46fe159603436a9ac3b003ac Signed-off-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-on: https://git-master/r/1512565 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: rename gk20a_pmu_cmd_post()Mahantesh Kumbar2017-07-05
| | | | | | | | | | | | | | | - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: PMU reset reorgMahantesh Kumbar2017-06-29
| | | | | | | | | | | | | | | | | | | | | | | | - nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvpgu: Remove FECS override sysfs APITerje Bergstrom2017-06-27
| | | | | | | | | | | FECS override PMU support was removed with http://git-master/1297370. Remove the sysfs API that is wired to that. Change-Id: I5802e5a8dd78b80c3d255dd93587b24df9203fca Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master/r/1507934 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use nvgpu_flcn_* interfacesMahantesh Kumbar2017-06-23
| | | | | | | | | | | | | | - set nvgpu_flcn_reset() to point to gk20a_pmu_reset() - set PMU interrupt using nvgpu_flcn_enable_irq() - replace pmu_idle with nvgpu_flcn_wait_idle() JIRA NVGPU-57 Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1469478 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: use fuse APIs from <nvgpu/fuse.h>Deepak Nibade2017-06-15
| | | | | | | | | | | | | | | | | | | | | | | | Remove <soc/tegra/fuse.h> includes and include <nvgpu/fuse.h> header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: reorganize PMU initMahantesh Kumbar2017-06-12
| | | | | | | | | | | | | | | | | | | | | | | | - Moved PMU init code from pmu_gk20a.c to "drivers/gpu/nvgpu/common/pmu/pmu.c" file - Moved below related methods SW/HW init, init msg handler, deinit/destroy, PMU state machine -Created HAL methods to read message queue tail & supported mutex count. -prepend with nvgpu_ for pmu init global mehtods JIRA NVGPU-56 JIRA NVGPU-92 Change-Id: Iea9efc194fefa74fb5641d2b2f4633577d2c3a47 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1480002 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: reorganize PMU IPCMahantesh Kumbar2017-06-09
| | | | | | | | | | | | | | | | | | | | - Moved PMU IPC related code to drivers/gpu/nvgpu/common/pmu/pmu_ipc.c file, -Below is the list which are moved seq mutex queue cmd/msg post & process event handling NVGPU-56 Change-Id: Ic380faa27de4e5574d5b22500125e86027fd4b5d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1478167 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: moved & renamed "struct pmu_gk20a"Mahantesh Kumbar2017-06-05
| | | | | | | | | | | | | | | | | | | - Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: gm20b: Use new delay APIsTerje Bergstrom2017-04-13
| | | | | | | | | | | | | | | Use platform agnostic delay functions instead of Linux kernel APIs. This allows removing dependency to Linux header linux/delay.h. At the same time remove #include lines for other unused Linux headers. JIRA NVGPU-16 Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1460114 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gm20b: Use new error macrosTerje Bergstrom2017-04-07
| | | | | | | | | | | | | | | gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ic27fb98e03a982e5a1cf672cb4e8f87ecea10a5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457345 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* drivers: gpu: nvgpu: Use soc/tegra/fuse.h for fuse headerLaxman Dewangan2017-01-19
| | | | | | | | | | | | | | | | The fuse headers are unified and moved all the content of linux/tegra-fuse.h to the soc/tegra/fuse.h to have the single fuse header for Tegra. Use unified fuse header soc/tegra/fuse.h. bug 200260692 Change-Id: Icab3ba5c3dbcd3fa831455c2f336942d356ff5ac Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1287498 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.Deepak Goyal2017-01-18
| | | | | | | | | | | | | | pmu_queue_head() & pmu_queue_tail() are updated to use gops to include chip specific PMU queue head/tail registers. JIRA GV11B-30 Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747 Signed-off-by: Deepak Goyal <dgoyal@nvidia.com> Reviewed-on: http://git-master/r/1283266 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: Use timer API in gm20b codeAlex Waterman2017-01-18
| | | | | | | | | | | | | | | Use the timer API instead of Linux specific APIs for handling timeouts. Also, lower the L2 timeout from 1 second (absurdly long) to 5ms. Bug 1799159 Change-Id: I27dbc35b12e9bc22ff2207bb87543f76203e20f1 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1273825 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: HAL to query LPWR feature supportMahantesh Kumbar2017-01-16
| | | | | | | | | | | | | | | HAL to query LPWR feautre's RPPG/MSCG support based on current pstate configured. JIRA DNVGPU-71 Change-Id: I58a34c6dca68e3eb76e222bd781578bf682eac34 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1283916 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
* gpu: nvgpu: Move gm20b HW headersAlex Waterman2017-01-11
| | | | | | | | | | | | | | | | | | | | Move the gm20b HW headers to a new directory specially for them: include/nvgpu/hw/gm20b And change the code to include like so: #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I0765e2f6bcd5aa1e803efd250056de3cf9bfa7ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244791 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: MSCG supportMahantesh Kumbar2016-12-26
| | | | | | | | | | | | | | | | | | | | | | | | | - Added enable_mscg, mscg_enabled & mscg_stat flags, mscg_enabled flag can be used to controll mscg enable/disable at runtime along with mscg_stat flag. - Added defines & interface to support ms/mclk-change/post-init-param - Added defines for lpwr tables read from vbios. - HAL to support post init param which is require to setup clockgating interface in PMU & interfaces used during mscg state machine. - gk20a_pmu_pg_global_enable() can be called when pg support required to enable/disable, this also checks & wait if pstate switch is in progress till it complets - pg_mutex to protect PG-RPPG/MSCG enable/disable JIRA DNVGPU-71 Change-Id: If312cefc888a4de0a5c96898baeaac1a76e53e46 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247554 (cherry picked from commit e6c94948b8058ba642ea56677ad798fc56b8a28a) Reviewed-on: http://git-master/r/1270971 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: PG engines init/allow/disallow updateMahantesh Kumbar2016-12-20
| | | | | | | | | | | | | | | | | | | | | | | - pmu_init_powergating loops & init multiple PG engines based on PG engines supported - generalize pg init param HAL to support multiple PG-engine init based on PG engine parameter - HAL's to return supported PG engines on chip & its sub features of engine. - Send Allow/Disallow for PG engines which are enabled & supported. - Added defines for pg engines JIRA DNVGPU-71 Change-Id: I236601e092e519a269fcb17c7d1c523a4b51405f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247409 (cherry-picked from commit 1c138cc475bac7d3c3fbbd5fb18cfcb2e7fdf67a) Reviewed-on: http://git-master/r/1269319 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* gpu: nvgpu: change the usage of tegra_fuse_readlShardar Shariff Md2016-09-13
| | | | | | | | | | | | | | | tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: I01f23cfafd5923d86ac48e67b36132ce690e962b Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/1217374 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
* gpu: nvgpu: update HAL of ACR BLMahantesh Kumbar2016-06-01
| | | | | | | | | | | | | -update HAL of ACR BL which can support gm204/gm206 and DMATRFBASE method to global JIRA DNVGPU-10 Change-Id: I56fc7ce040dadb6473f6f375ee6ce90783a046ad Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1154954 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu:nvgpu:gm20b: update elpg prod settingsVijayakumar2016-05-24
| | | | | | | | | | | | | | | | | | | | | bug 1764398 PGSequencer settings use index to writ to PSORDER register setting. HW has implementation for 28 PSORDER (PSORDER0 - 27). Every write will auto increment index and index will wrap around after it reaches 27. In PROD settings we are writing enable for 0 to 27 and zero for 28 to 65. This overwrites enables written to 0 to 27. Effectively those partitions are never power gated. P4 SWCL# 20744424 Change-Id: I45826e98dd6a84e9c4fe119fbe7ca75acfd8a4ea Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1149055 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add HAL op for PMU resetTerje Bergstrom2016-05-20
| | | | | | | | | Sequence to reset PMU is different for iGPU and dGPU. Specialize and implement iGPU version. Change-Id: I5b9ff2c018a736bc9e27b90d0942c52706b12a12 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1150540
* gpu: nvgpu: Add Fuse prints on PMU HaltSupriya2016-04-06
| | | | | | | | | | | | | | | | -Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: I59f5fcf4a69bdd2a2eea81a69dd99bb9c4c21e1d Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1113464 (cherry picked from commit d0320eed72c5070c4fcc7564c02fa38599984751) Reviewed-on: http://git-master/r/1120429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: LRF, TEX, LTC, DRAM overrideSupriya2016-02-26
| | | | | | | | | | | | - Adding support for FECS mem overrides Bug 1699676 Change-Id: I6c9ddcd98d57b29059513ee508c6f92b194c4fc7 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/921253 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: ELPG init & statistics updateMahantesh Kumbar2015-09-30
| | | | | | | | | | | | | | | | - Required init param to start elpg - change in statistics dump Bug 1684939 Change-Id: I26dca52079f08b8962e9cb758831910207610220 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/802456 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/806179 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: HAL to write DMATRFBASEMahantesh Kumbar2015-09-15
| | | | | | | | | | Bug 200137618 Change-Id: I18b980876e93c3f7287082701e1d2b998cd33114 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/798777 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Fix NS boot transcfgSupriya2015-08-21
| | | | | | | | | | | | | Bug 1667322 Accommodate for transcfg address change Change-Id: I7054202b8ce3be1a3fbfe0465e662be6f9740eb3 Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/780326 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* nvgpu: gm20b: make local function 'static'Amit Sharma (SW-TEGRA)2015-07-10
| | | | | | | | | | | | | | | Fixed the following sparse warning by making the local function 'static': - warning: symbol 'gm20b_load_falcon_ucode' was not declared. Should it be static? Bug 200067946 Change-Id: I11beaa301dc45dfec6f2295a6a96c1571e0264c9 Signed-off-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-on: http://git-master/r/766361 Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-on: http://git-master/r/767991 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: load secure gpccs using dmaVijayakumar2015-06-26
| | | | | | | | | | | | | | | | | | bug 200080684 use new cmd defined in ucode for loading GR falcons. flip PRIV load flag in lsb header to indicate using dma. use pmu msg as cmd completion for new cmd instead of polling fecs mailbox. also move check for using dma in non secure boot path to hal. Change-Id: I22582a705bd1ae0603f858e1fe200d72e6794a81 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/761625 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: add secure gpccs boot supportVijayakumar2015-05-18
| | | | | | | | | | | | | | | | | bug 200080684 keeping it disabled by default also trimming the code by removing redundant variable to check recovery. pmu quick wait now checks only for irqs which are serviced by kernel. requests pmu to bit bang gpccs ucode. Change-Id: I12ef23d6d59b507e86a129b69eab65b21d0438c6 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/729622 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: made gm20b_pmu_init_acr() global.Mahantesh Kumbar2015-04-27
| | | | | | | | | | | | | | | | | | -made gm20b_pmu_init_acr() method to global to access in pmu-T18x. Bug 200085428 Change-Id: Ic262997d5c6f97cecf12d17d9a64a9d1cd20c83b Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/732210 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/735727 Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Tested-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* gpu:nvgpu:gm20b: update pg sequencer dataVijayakumar2015-03-18
| | | | | | | | | | | | | | bug 1553301 sequencer data picked up from p4sw #19041893 Change-Id: I3d05972201572e3db31d1b46e93c03dda3e58d54 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/657023 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* gpu: nvgpu: gm20b: Support secure FECS recoveryVijayakumar2015-03-18
| | | | | | | | | | | | | When falcons are secured use PMU commands to reload FECS firmware. Bug 200042729 Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/552544 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 22:17:13 -0400