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* gpu: nvgpu: Set compression page per SoCTerje Bergstrom2015-04-04
| | | | | | | | | | | | | Compression page size varies depending on architecture. Make it 129kB on gk20a and gm20b. Also export some common functions from gm20b. Bug 1592495 Change-Id: Ifb1c5b15d25fa961dab097021080055fc385fecd Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/673790
* gpu: nvgpu: Per-alloc alignmentTerje Bergstrom2015-03-18
| | | | | | | Change-Id: I8b7e86afb68adf6dd33b05995d0978f42d57e7b7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/554185 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: fix sparse warningsDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Fix below sparse warnings : warning: Using plain integer as NULL pointer warning: symbol <variable/funcion> was not declared. Should it be static? warning: Initializer entry defined twice Also, remove dead functions Bug 1573254 Change-Id: I29d71ecc01c841233cf6b26c9088ca8874773469 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/593363 Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sachin Nikam <snikam@nvidia.com>
* Revert "gpu: nvgpu: GR and LTC HAL to use const structs"Sam Payne2015-03-18
| | | | | | | | | | | This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e. Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94 Signed-off-by: Sam Payne <spayne@nvidia.com> Reviewed-on: http://git-master/r/592221 Tested-by: Hoang Pham <hopham@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban <mluban@nvidia.com>
* gpu: nvgpu: GR and LTC HAL to use const structsTerje Bergstrom2015-03-18
| | | | | | | | | | | Convert GR and LTC HALs to use const structs, and initialize them with macros. Bug 1567274 Change-Id: Ia3f24a5eccb27578d9cba69755f636818d11275c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590371
* gpu: nvgpu: Split L2 size calculation per chipTerje Bergstrom2015-03-18
| | | | | | | | | | gk20a and gm20b calculate L2 size with different parameters. Split the function for calculating size so that it does not query GPU id. Bug 1567274 Change-Id: I09510c1bf0286c9df125d74e51df322c32bde646 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Fix build warningsTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Disable illegal compstat access intrTerje Bergstrom2015-03-18
| | | | | | | | | | | | | | | | Disable illegal compstat access interrupt. We access compstat backing store to handle CDE swizzling. Also change the magic number for evicted_cb to use a generated value. Change-Id: I79b299abbffcb90497690ba4fc55d8517a3dbd87 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/496444 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Jussi Rasanen <jrasanen@nvidia.com> Tested-by: Jussi Rasanen <jrasanen@nvidia.com>
* gpu: nvgpu: Fix max comptag calculationTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix order of calculation for max comptag line calculation. Bug 1549451 Change-Id: I13bf657f0f0b8aafa4d64dacacb74d7224fed379 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494657 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
* gpu: nvgpu: Fix and enable L2 error processingTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Fix L2 error processing to look into interrupts in each L2 and slice. Enable L2 error interrupts. Bug 1549451 Change-Id: If6dd77f1333426a10b6a148c9432c12df8d879c7 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/494656 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
* TEMP: gpu: nvgpu: gm20b: Mask LTC interruptsArto Merilainen2015-03-18
| | | | | | | | | | | LTC interrputs were set to random values at boot. For now, disable all interrupts. Change-Id: Ibb032cac91d3ea9a951fd8c2eb62a783af5bd1a1 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/482639 Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
* gpu: nvgpu: manage phys pages at runtimeDeepak Nibade2015-03-18
| | | | | | | | | | | | | | | | | | | Current implementation is based on config GK20A_PHYS_PAGE_TABLES to have APIs to create/free/map/unmap phys pages Remove this config based implementaion and move the APIs so that they are called at runtime based on tegra_platform_is_linsim() In generic APIs, we first check if platform is linsim and if it is then we forward the call to phys page specific APIs Change-Id: I23eb6fa6a46b804441f18fc37e2390d938d62515 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/488843 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Comptag size must use LTC countTerje Bergstrom2015-03-18
| | | | | | | | | | | Calculation for comptag backing store must use number of LTCs instead of number of FBPs. Change-Id: If0aa636e09a3d24459987e626fe53bb7c96f1b15 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/453809 Reviewed-by: Shridhar Rasal <srasal@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com>
* gpu: nvgpu: gm20b: Store LTC configurationArto Merilainen2015-03-18
| | | | | | | | | Change-Id: Ia780e6a7cb3579f0d6ed2dca9949a349799535fd Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/448115 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: fix CBC clearWei Sun2015-03-18
| | | | | | | | | | | | | | | gm20b_ltc_cbc_ctrl sent the wrong register value to clear the CBC. Bug 1507804 Change-Id: Ib0d867a122466e50cb15fef3b320fb2ee8455ef2 Signed-off-by: Wei Sun <wsun@nvidia.com> Reviewed-on: http://git-master/r/435297 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
* gpu: nvgpu: Wait for CBC op to finish for all LTCsTerje Bergstrom2015-03-18
| | | | | | | | | | | We broadcast CBC operation to all LTCs, but we wait for only one to finish. Bug 1507804 Change-Id: Ib10aa5fe3a34b31862b2d5162c77441f7444a7ba Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/428123
* gpu: nvgpu: Add timeout to L2 flushAlex Waterman2015-03-18
| | | | | | | | | | | | Add a timeout mechanism to the L2 flushing code for gm20b. Previously the code could spin forever in a loop if some issue were to occur with the L2 causing the flush to fail. Change-Id: I742c7671bac92aeb8e9674c43d30c45b2de4a836 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/423842 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement L2 flush in fifo recoveryAlex Waterman2015-03-18
| | | | | | | | | | | | | Implement a full L2 flush (clean and invalidate) for gm20b in the fifo recovery path. Bug 1512176 Change-Id: Ibf89ede9cca65a6868ebff89825869053302a007 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/416435 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Reload ZBC values on rail gate exitTerje Bergstrom2015-03-18
| | | | | | | | | | | When exiting rail gate, we reloaded default ZBC values. The correct behavior is to reload the values. Bug 1447255 Change-Id: I7aad3586dda91a91a3629062a27001af281b955e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/418346
* gpu: nvgpu: gm20b: fix compression sharingKevin Huang2015-03-18
| | | | | | | | | | | | | | | | For GM20B alone, the LTC count is already accounted for the HW logic for the CBC base calculation from the postDivide address. So SW doesn't have to explicity divide it by the LTC count in the postDivide address calculation. Bug 1477079 Change-Id: I558bbe66bbcfb7edfa21210d0dc22c6170149260 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/414264 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Implement ELPG flush for gm20bTerje Bergstrom2015-03-18
| | | | | | | | | | | ELPG flush is initiated from a common broadcast register, but must be waited on via per-L2 registers. Split gk20a and gm20b versions of the flush. Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/401545 Reviewed-by: Automatic_Commit_Validation_User
* gpu: nvgpu: gm20b: add ltc isrKevin Huang2015-03-18
| | | | | | | | | | Bug 1507804 Change-Id: Ic58e21f4d995cf4f4fc7bb5fc6ec84a6c4d25d46 Signed-off-by: Kevin Huang <kevinh@nvidia.com> Reviewed-on: http://git-master/r/403214 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: gm20b: Alloc phys mem for CBC in simArto Merilainen2015-03-18
| | | | | | | | | | | | | | | CBC frontdoor access works incorrectly in the simulator if CBC is allocated from IOVA. This patch makes CBC allocation to happen from physical memory if are running in simulator. Bug 1409151 Change-Id: Ide08f4eab6911adc5737001c6d751ee227fec8f9 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/401544 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gnu: nvgpu: gm20b: CBC clean and invalidateBo Yan2015-03-18
| | | | | | | | | the CBC clean and invalidate is done for gk20a for bug 1409151, now it's time to do the same fo gm20b. the text of this change is strictly copied from gk20a, simply to make build pass. Change-Id: Id717cb1e2ca0fa3f8483c3fd40d7629a9cc85ec9 Signed-off-by: Bo Yan <byan@nvidia.com>
* gpu: nvgpu: Add GPU driver for GM20BBo Yan2015-03-18
this moves GM20B driver to the new location Change-Id: I5fde14e114a8db79738a4c61849912b1ae225fb5
generated by cgit v1.2.2 (git 2.25.0) at 2024-08-26 15:55:45 -0400