| Commit message (Collapse) | Author | Age |
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LTC interrputs were set to random values at boot. For now, disable
all interrupts.
Change-Id: Ibb032cac91d3ea9a951fd8c2eb62a783af5bd1a1
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/482639
Reviewed-by: Lauri Peltonen <lpeltonen@nvidia.com>
Tested-by: Lauri Peltonen <lpeltonen@nvidia.com>
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ltc_ltc0_lts0_cbc_ctrl1_r() was pointing to broadcast register.
Change-Id: I1646f6c68ac944333474029bb78242844424c6f7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/428919
Reviewed-by: Matt Craighead <mcraighead@nvidia.com>
Tested-by: Matt Craighead <mcraighead@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
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Add the necessary cache management registers for doing a
full L2 flush in GM20b.
Bug 1512176
Change-Id: I7799e5e584238a0af02abbf4f49917d7590d97dc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/417260
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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ELPG flush is initiated from a common broadcast register, but must be
waited on via per-L2 registers. Split gk20a and gm20b versions of
the flush.
Change-Id: I75c2d65e8da311b50d35bee70308b60464ec2d4d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/401545
Reviewed-by: Automatic_Commit_Validation_User
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the CBC clean and invalidate is done for gk20a for bug 1409151, now
it's time to do the same fo gm20b. the text of this change is
strictly copied from gk20a, simply to make build pass.
Change-Id: Id717cb1e2ca0fa3f8483c3fd40d7629a9cc85ec9
Signed-off-by: Bo Yan <byan@nvidia.com>
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this moves GM20B driver to the new location
Change-Id: I5fde14e114a8db79738a4c61849912b1ae225fb5
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