summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
Commit message (Collapse)AuthorAge
* gpu: nvgpu: add accessors for global_esr values and sm_dbgr_controlDeepak Nibade2016-04-19
| | | | | | | | | | | | | Add gk20a/gm20b accessors for various global_esr values and for sm_dbgr_control modes Bug 200156699 Change-Id: If7fd8cd7567f8bcd1f645facf9553bdc0a153526 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1120333 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: hw definitions for FECS trace on gm20bThomas Fleury2016-04-07
| | | | | | | | | | | | Bug 1648908 Change-Id: I3b9a1ebaf062f15db397acd81b8312dc8daa9193 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1117262 Reviewed-on: http://git-master/r/1121233 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Sync with register generatorTerje Bergstrom2016-04-07
| | | | | | | | | Use re-generated register definitions. This synchronizes kernel with the register generator. Change-Id: I85a00f8f5c7bdfbc56cf4df909e5ae892d86f062 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1120812
* gpu: nvgpu: API to extract context idDeepak Nibade2016-01-13
| | | | | | | | | | | | | Add new API gr_gk20a_get_ctx_id() to get/extract context id from GR context Bug 200156699 Change-Id: If0e8887a9a6b139cd795bf03f5def64fd664d12b Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/927130 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Add CDE bits in FECS headersujeet baranwal2015-09-29
| | | | | | | | | | | | | | | | In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B aligned, otherwise causes a HW deadlock. Gpu driver makes changes in FECS header which FECS uses to configure the T1 promotions to aligned 128B accesses. Bug 200096226 Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/804625 Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
* Revert "gpu: nvgpu: Add CDE bits in FECS header"Terje Bergstrom2015-09-24
| | | | | | | | This reverts commit 882975f7f1b4e050be79b0a047a2daa8b53a9187. Change-Id: I4940fc9f7a837840be1ea8e42d58d603235d88d5 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/804616
* gpu: nvgpu: Add CDE bits in FECS headersujeet baranwal2015-09-24
| | | | | | | | | | | | | | In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B aligned, otherwise causes a HW deadlock. Gpu driver makes changes in FECS header which FECS uses to configure the T1 promotions to aligned 128B accesses. Bug 200096226 Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995 Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/802327 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Allow enabling PC samplingTerje Bergstrom2015-04-04
| | | | | | | | | | | | Allow enabling of PC sampling hardware workaround. It is only applicable to gm20b. Bug 1517458 Bug 1573150 Change-Id: Iad6a3ae556489fb7ab9628637d291849d2cd98ea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/710421
* gpu: nvgpu: Update gk20a and gm20b headersSeshendra Gadagottu2015-04-04
| | | | | | | | | | | | | | | Update gk20a and gm20b headers with bar2 register block registers. Also updated gm20b ctxsw headers with latest tool output. Bug 1587825 Change-Id: I9d1c459e03051278e7e79806803aaf71655f0dc5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/672124 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Pre-Population of zbc entriessujeet baranwal2015-04-04
| | | | | | | | | | | | | | | | | | | | The default zbc entries were never populated in zbc HW table because the conditional flag "gr->sw_ready" was always set thus avoided the zbc default loading function call. Now zbc default loading would happen only during boot time in sw structure.Hw zbc regs would be loaded from that structure every time a railgate exit happens. Bug 1580210 Change-Id: Ie3e40738cbc84cf724c3f3871f15b17a5c84025a Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com> Reviewed-on: http://git-master/r/662306 Reviewed-by: Sami Kiminki <skiminki@nvidia.com> Tested-by: Lauri Peltonen <lpeltonen@nvidia.com> Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
* gpu: nvgpu: Sync gk20a and gm20b headersTerje Bergstrom2015-03-18
| | | | | | | | | | | | | Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
* gpu: nvgpu: Add GPU driver for GM20BBo Yan2015-03-18
this moves GM20B driver to the new location Change-Id: I5fde14e114a8db79738a4c61849912b1ae225fb5
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-17 01:27:49 -0400